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Q2FY24TessentAI 800X100 
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Siemens EDA
Posted on by Beth Martin

Mentor at TSMC OIP, 16nm, and 10nm

Mentor at TSMC OIP, 16nm, and 10nm
by Beth Martin on 09-26-2014 at 4:46 pm
Categories: Siemens EDA

On Tuesday, September 30, TSMC hosts another Open Innovation Platform Ecosystem forum at the San Jose Convention Center. Have you registered? This year includes 30 technical sessions from TSMC’s ecosystem partners, divided into three separate tracks. I’ll be hanging out in the EDA track, listening to various takes on 16nm FinFET process design issues and marveling at the prospect of 10nm.

Mentor has three sessions:

  • “Design and Verification of 2.5D/3D IC Architectures Using TSMC 16nm FinFET Technology,” Mentor Graphics
  • “Four Ways an ECO Fill Reference Flow Can Benefit Your Bottom Line,” Mentor Graphics and TSMC
  • “Maintaining Hierarchy and Accuracy for Post-Layout Simulation: Grey/Black Box Flows in LVS->PEX->Simulation,” Oracle and Mentor Graphics.

Your friends at Mentor have made a videoabout working with TSMC on 10nm, and also have a press release out today about it.

It’s interesting to see engineering work turn towards 10nm when I’m not used to the idea of 16nm, but thus is the never ending march of technology, right? I look forward to learning more at the forum.

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