An Imaginative Approach to AI-based Design

DVCon 2025 was unquestionably a forum for pulling out all the stops in AI-based (RTL) design and verification, particularly around generative AI and agentic methods. I heard three product pitches and a keynote and have been told that every AI talk was standing room only. A pitch from Rise-DA particularly appealed to me because they have clearly taken care to balance intelligently between the promise of AI, the pros and cons of abstraction and the real dynamics of introducing new methods into established and proven flows and training.

Abstraction made easy for designers, and for training

Given the heritage of Rise-DA, it shouldn’t be surprising that abstraction is important to this story. The CEO, Badru Agarwala, was GM of the Calypto System Division at Mentor; high-level design/synthesis is in his DNA. Yet C/C++ HLS is still a barrier to adoption for most RTL designers. Rise-DA simplifies adoption by adding untimed/loosely timed SystemVerilog as a supported behavioral description. Rise also supports mixed language, allowing for reuse across multiple design styles.

The second key idea concerns training. A challenge in applying LLMs to RTL design in any capacity is that the code-corpus on which a tool can train is much smaller than for software, further reduced since no enterprise wants to share their trade secrets. Commonly a design team can train on their own RTL corpus, maybe adding some very generic training from the tool vendor. Hardly an extensive training set for generative AI.

However a high-level design tool can train on the full software corpus – C, C++, Python and more. There are some restrictions for synthesis which should be recognized, but those can be handled in fine-tuning and in linting to catch any escapes. What about synthesis from SystemVerilog – doesn’t that run into the same RTL corpus problems? According to the Rise folks the syntax you will use in synthesizable behavioral SV is (modulo some syntactic sugar) little different from that you would use in C/C++. So SV users in this context benefit from the same extensive software corpus training.

Connecting to production tooling through agents

Remember this is a high-level synthesis system. You’re going to use this flow to design new building blocks or subsystems from scratch. These might be for video/audio/radar/lidar pipelines or custom DNNs (or possibly a multi-layer perceptron). CPUs/GPUs/systolic arrays might be possible in principle but don’t play to the strengths of HLS.

The Rise flow will generate synthesizable RTL from your behavioral input, first through well-known HLS transformations (loop unrolling, pipeline scheduling, parallelism, etc.), then through technology/implementation mapping. Rise takes care of the first part, and they have integrated the Google XLS platform for the second part (in this context XLS is Google’s name for accelerated synthesis).

This flow is designed to be fast and lightweight, in support of fast turnaround synthesis/ implementation experiments to gauge performance and PPA. The Rise folks provided a couple of interesting insights here. They say this is “screaming fast”, allowing for a lot of experimentation to find optimal solutions. A designer might counter that ultra-fast synthesis can’t be very optimized; isn’t this a problem? Rise would agree for the early days when HLS was introduced, however today all that optimization can be left to production synthesis tools which are much better at handling that level of implementation detail.

To validate correctness and optimality of generated solutions the flow must run production tools like synthesis or RTL simulation. This is handled through agents which will launch said tools as and when you require. Rise will feedback estimates like PPA to provide you with insight on how you want to tune the high level.

For verification, you will want to validate that generated RTL works the same way as the behavioral source against the behavioral tests you have been using in algorithm development. Rise instruments the generated RTL with transactors so you can plug the generated RTL back into those behavioral sims to check correspondence.

You can also add asserts, cover statements, even display statements, to your HLS model, which will be mapped through to the RTL in support of UVM-based testing. Rise will also add SV attributes (if requested) to the RTL to help you trace back and forth when you’re trying to localize a problem. All providing aids to help you localize mismatches or unexpected behavior, as a guide to further refining the HLS model.

Now add GenAI

With a solid foundation and training scope that can leverage the full range of learning drawn from software engineering, you might understand why I find this direction appealing. Rise supports the kinds of generative code development you might see in a CoPilot platform –statement completion, prompt-based code snippet generation, and retrieval-augmented generation (RAG) to find real code examples, documentation, test suggestions, etc. I believe RAG feedback is limited to customer in-house sources for obvious reasons.

I’m impressed. Well thought through, closely coupled to production tools and a way for RTL designers to progress past the C/C++ barrier. (I suspect even that dam will break as more system enterprises demand flows better suited to their ecosystems.) You can learn more HERE.

Also Read:

CEO Interview: Badru Agarwala of Rise Design Automation

SemiWiki Outlook 2025 with yieldHUB Founder & CEO John O’Donnell

TRNG for Automotive achieves ISO 26262 and ISO/SAE 21434 compliance