You Get What You Measure – How to Design Impossible SoCs with Perforce

We all know that a trusted, reliable, and well-integrated design flow is critical to successful advanced SoC design. So is proven, robust IP. While these elements are necessary for success, they are not, by themselves, sufficient. There are other aspects to consider – measurement, tracking and coordination. We’ve all heard the phrase; you get what you measure. This concept is especially true for complex chip design. Without solid management of assets and tracking of processes and results, success will, at best, be a lucky break that is not repeatable. The tools and infrastructure needed for this phase of chip design is the topic of this post. Read on to learn how to design impossible SoCs with Perforce.

DevOps Meets Chip Design

DevOps combines software development (Dev) and IT operations (Ops). The goal is to shorten the development lifecycle and facilitate continuous delivery with high quality results. The practice began in software development but has expanded to cover many industries and processes. Perforce is a company that focuses on delivering these kinds of solutions across many markets and products. According to its website, Perforce is a leading supplier of highly scalable development and DevOps solutions designed to deliver dynamic development, intelligent testing, risk management, and boundaryless collaboration. A broad and bold mission. Their tagline leaves an even stronger impression. It’s shown in the graphic at the top of this post.

When it comes to market penetration there are more bold statements, like Perforce solutions are used by 75% of Fortune 100 companies to innovate at scale. What is particularly interesting to the SemiWiki readership is this statement: 9 of the top 10 semiconductor companies use Perforce to get ahead of the competition with the best designs.

What’s In It for Me?

There have been many posts about Perforce and its acquisition of Methodics on SemiWiki. Topics such as how to achieve scalability, how to plug holes in your IP portfolio and how to securely collaborate in the cloudfor example. Let’s step back a bit and look at the big picture. What is the product portfolio offered by Perforce to optimize chip design? I’ll explore some of that next. There is also a very informative podcast on the topic coming soon. More on that in a moment.

Let’s start with what kind of DevOps tools are needed for IC design. Here is a list that should resonate:

• IP and variant reuse and sharing
• IP bill of materials (BoM) management
• IP and design collaboration
• End-to-end traceability
• Design data management
• A single source of truth across design and development

I’m sure you can think of a horror story (or two) when one of the above items went wrong in a complex design project. It turns out Perforce has quite a rich product portfolio that addresses all the above issues. The company works similar magic for many other industries, including:

• Aerospace & defense
• Automotive
• Embedded systems
• Energy
• Financial
• Gaming
• Virtual production
• Government
• Medical devices
• Software
• Digital twins

That’s quite a list. With this many market challenges, the tools have become quite robust.  Regarding semiconductors, there are four key functional areas that form an integrated solution. They are:

IP Lifecycle Management: Track and manage IPs throughout their lifecycle.

Verification Traceability: Manage and provide end-to-end verification traceability.

IP Security Assurance: Find and track security threats in your SoC design.

Functional Safety: Ensure functional safety compliance with proven documentation.

You can even find a semiconductor starter pack on SemiWiki.

To Learn More

Beyond the solutions for mainstream semiconductor companies discussed so far, there is also a slightly different set of requirements and challenges faced by early-stage semiconductor companies. Dan Nenni and I recently caught up with Michael Munsey for a podcast. Michael is the senior vice president of marketing, business development and corporate strategy at Perforce, so he knows a thing or two about how to make chip design better.

We explored what specific challenges early-stage companies face with regard to IP management. What are the specific areas to focus on, what are the risks and what are the rewards?  It’s a compelling and informative conversation. The podcast will air on Friday, August 20. You can watch for it here. You’ll learn how to design impossible SoCs with Perforce.

Also Read

Achieving Scalability Means No More Silos

Your IP Portfolio is Probably Leaking. What Can You Do About It?

Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud