Very often we talk about increasing design complexities and verification challenges of SoCs. With ever growing design sizes and multiple IPs on a single SoC, it’s a fact that SoC design has become heterogeneous, being developed by multiple teams, either in-house or outsourced. Considering economic advantage amid pressure on profit margin, it makes sense for any fabless design company or an IDM to outsource the components which can be developed by any third party at lesser cost with good quality. However whether a component is done by a team in-house or outside, it must be checked for its qualifying criteria. This task is easier said than done as the list of these components can be long including IOs, cell libraries, IPs etc. And at the end overall SoC integration has to be done by an expert team. Even after drawing such importance, QA task does not attract fancy of designers who are more focused on developing new designs.
It’s interesting to know about a tool exactly for this purpose which enables everyone in the design chain to contribute to right quality of the design at different stages of its making. In other words the tool actually realizes TQM (Total Quality Management) of the chip by sharing responsibilities across all partners. Crossfire, developed byFractal Technologies, employs an integral approach to quality by letting designers do QA checks during the development of their own IPs or library cells, at the time of shipping them to other SoC teams and at the time of receiving any components from other teams, thus enabling quality by construction of SoC. This tool also enables the SoC integration team to provide the test sets to IP providers which they need to qualify before dispatching their IPs.
The tool is quite versatile in accommodating most of the formats of circuit description in front-end as well as back-end domain including any user defined format in ASCII text, HTML or PDF (converted to text) and presenting the results in easy-to-understand format and easy-to-use browsers. It constructs its own unified data model to maintain consistency and accuracy.
[A form representing cell library QA aspects]
During the QA check, it flags any mismatch which can be between simple terminal names or complex functionalities such as Boolean values or timing arcs. The unified data model is flexible to accommodate proprietary data such as characterization data and data sheets.
Above is an example of CCS (Synopsys Liberty) specific checks. For any format, all checks required to validate a library are provided that allows users to quickly configure test sets essential to qualify the database. Crossfire also provides APIs for users to add their own customized checks.
Crossfire assists CAD teams to build partial test sets at various stages of design from the beginning, thus eliminating any backtracking, re-work or duplication of work and improving productivity. As an example, it first checks pin compatibility of layout, schematic and underlying format / database before going into further verification.
In case of IPs, Crossfire is optimized to deal with large data in terms of GDS or Verilog and is made intelligent to check compatibility with language dialects such as Verilog-A. As IP models can be delivered in various forms such as hard macro (GDS) or synthesizable IP (RTL), Crossfire makes sure that only appropriate checks are made for those, thus eliminating unnecessary tests. For example, at GDS, routing checks are relevant while those at RTL do not make sense. Conversely at RTL, tests can be done by running a few samples at relevant stages of the design flow. Crossfire can generate final QA report of an IP which can be delivered along with the IP to the IP customer or SoC team.
The report provides the summary of what passed and what failed with required explanation for waiving them. The QA reports and test sets make it possible for the SoC integrators to quickly determine about the acceptance of the IP affront without leaving any chance of discovery later in the cycle.
Crossfire plays a key role in quality checks from the very beginning of the design stages to the final integration, thus making sure that quality is in-built into the design. This automates the process, eliminates any re-work and assures predictable completion of SoC. It ensures that suppliers, consumers and other stake holders share responsibility towards quality of the final SoC. A white paper with a detailed description of the tool and processes can be found at Fractal website HERE.