WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 595
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 595
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
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WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 595
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 595
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
Cadence
Posted on by Daniel Payne

A Mixed-Signal IC Summit in San Jose

A Mixed-Signal IC Summit in San Jose
by Daniel Payne on 10-03-2013 at 9:26 am
Categories: Cadence, EDA

Analog and mixed-signal ICs are tougher to design and verify compared to digital, so if you want to learn more about best practices from actual AMS engineers then consider attending a summitthat is sponsored by Cadence Design Systems next Thursday, October 10th in San Jose from 8:00AM until 6:30PM.

They’ve lined up an interesting mix of presenters from: Academia, Industry, Foundry (TSMC), Cadence R&D, Freescale, Cirrus Logic, STMicroelectronics, Microsemi, Rambus. You’ll be served breakfast, lunch and enjoy a social time after the presentations.

Agenda

  • 08:30-09:30am Registration and Breakfast
  • 09:30-09:45am Welcome and Opening Remarks by Dr. Chi-Ping Hsu, Sr. VP R&D and Chief Strategy Officer, Cadence
  • 09:45-10:30am Academic Keynote: Challenges in Emerging Mixed-Signal Systems and Applications by Prof. Terri S. Fiez, Professor & Head EECS Dept, Oregon State University
  • 10:30-11:15am Industry Keynote by Geoff Lees, Senior Vice President and General Manager Microcontrollers, Freescale
  • 11:15-11:30am Break
  • 11:30-12:00pm Mixed-Signal Trends-Foundry View by Douglas Pattullo, Technical Director, TSMC North America
  • 12:00-12:30pm Mixed-Signal Solutions Update by Koorosh Nazifi, Group Director, Initiatives R&D, Cadence
  • 12:30-01:30pm Lunch with R&D
  • 01:30-02:00pm Mixed-Signal Verification Methodology using Real Number Models by Tim Pylant(Cadence) & Bhupi Manola(Cirrus Logic)
  • 02:00-02:30pm Methodology for Verifying SerDes Bit-Error-Rate Using Real Number Modeling by Michael Hufford, Staff Design Engineer, Cadence
  • 02:30-03:00pm Cadence-Mixed-signal Implementation Update by Steven Lewis, Product Marketing Director, Analog/Custom Marketing, Cadence
  • 03:00-03:30pm Virtuoso Mixed-signal “Smart Power” Implementation Flow (case study) by Livio Fratantonio, STMicroelectronics
  • 03:30-03:45pm Break
  • 03:45-04:15pm Micro-Semi: OA Based Netlist on Top Flow(Case Study) by John M. Williams, Director of CAD Engineering, Microsemi IC Group, Microsemi
  • 04:15-04:45pm Interoperable Database for Mixed-Signal Designs Netlisting by Mark Snowden, CAD Manager, Rambus
  • 04:45-05:15pm Mixed-Signal IP Offerings by Cadence IP Team
  • 05:15-05:20pm Concluding Remarks & Raffle Drawing
  • 05:20-06:30pm Social Hour and Networking

Summary
This summit looks useful for practicing engineers because the presenters are mostly AMS engineers (only one marketing guy) or developers talking about approaches that they have used on actual chips. There is a registration process that you need to fill out for the Summit.

lang: en_US

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