
A few weeks ago, I had the chance to work with AMIQ EDA as they introduced a new product: DVT MCP Server. I was quite intrigued by the role it will play in AI-assisted chip design and verification, so I wanted to learn more. I spoke with Gabriel Busuioc, the AI Assistant team leader at AMIQ EDA, to understand more about the product and how their users will benefit from it.
Busu, it is great to talk with you. What is your role?
I have worked at AMIQ EDA for almost five years now. I started as an intern and joined full-time after I earned an MS in Advanced Software Services from the Politehnica University of Bucharest. I’ve worked on several very interesting projects, adding new features to our existing products as well as developing this new product.
What was the motivation for DVT MCP Server?
As you know, we provide integrated development environments (IDEs) and related tools for hardware design and verification. We support a wide range of languages, all of which we compile and elaborate. We connect together the code from hundreds or thousands of files into a single internal database of the complete hierarchical design and verification environment. That database gives us the ability to enable very smart editing, automated analysis and linting, debugging, documentation generation, and more.
This compiled database is internal to your Design and Verification Tools (DVT) products, correct?
Yes, and that’s where DVT MCP Server comes in. We started to wonder whether other tools, specifically AI agents, could benefit if they had access to project information within our internal database. It turned out that there is an open industry standard called Model Context Protocol (MCP) that serves exactly this purpose. It’s designed to connect AI agents to external data and applications. The goal is to make AI results more accurate by providing access to specialized or application-specific knowledge that was not learned through general training.
That sounds like the sort of knowledge in your database.
Exactly. We have detailed knowledge of design and verification languages plus of course the project-specific knowledge of the design and verification environment. DVT MCP Server allows all sorts of other applications to benefit from our knowledge and invoke our analysis engines.
Can you please give an example of how this might work?
Many engineers are experimenting with using AI to generate code, including for design and verification environments. They’re finding that AI agents are more effective with general-purpose languages than domain-specific languages. Limited training data and lack of context means that AI may hallucinate or generate incorrect code. DVT MCP Server provides quick, compiler-backed feedback to ground AI reasoning in accurate language semantics and their project context while detecting any errors in generated code.
So the benefit to users is better design and verification code?
Yes, that is what our users are reporting. If an AI agent makes a subtle language error, or incorrectly references part of the design or testbench, DVT MCP Server catches that and reports it back to the agent. Users don’t need to pay attention to errors that happen internally; all they see is correctly generated code. AI agents can understand, generate, modify, debug, and correct code for real-world design and verification projects efficiently and accurately. This is simply not possible using only generic training data.
What else should we know?
DVT MCP Server supports Verilog, SystemVerilog, VHDL, and the e language, so it covers the most widely used languages for chip development. It can run within DVT IDE to provide live project context to interactive AI assistants, or operate in batch mode to support fleets of AI agents in automated workflows.
Is this related to AI Assistant that you introduced in late 2024?
You can think of them as complementary. AI Assistant runs within our products, enabling users to generate, modify, and understand code more easily. It relies on our internal design and verification database. DVT MCP Server provides external access to information in this same database for other tools to yield better results.
Is there anything new with AI Assistant?
Yes. We originally introduced this feature for DVT IDE, but have now integrated it with all our products. For example, it enables Verissimo SystemVerilog Linter to better explain and auto-correct linting failures in design and verification code. AI Assistant also helps Specador Documentation Generator produce description comments, for example to fully document a module or entity, including all ports and signals. Moreover, we’ve enhanced AI Assistant within DVT IDE with a new Agentic profile that enables the connected LLM to autonomously get project information and do file edits end-to-end. All the users have to do is specify their requests in plain, natural language.
How can our readers learn more?
You can start with our product page, and then request a demo or an evaluation license. You can also meet with members of our team in person at DVCon U.S. in Santa Clara March 2-5, where we will be exhibiting at Booth 204. We hope to talk with you there or online.
Busu, thank you very much for your time. AI and AMIQ EDA are two great topics to discuss.
I agree, and I think they’re even more exciting when combined. Thank you, Tom.
Also Read:
2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
Runtime Elaboration of UVM Verification Code
Better Automatic Generation of Documentation from RTL Code
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