CDC Verification: A Must for IP and SoCs

In the modern SoC era, verification is no longer a post-design activity. The verification strategy must be planned much earlier in the design cycle; otherwise the verification closure can become a never ending problem. Moreover, verification which appears to be complete may actually be incomplete because of undetected issues which can resurface during tape-out or even in the field after fabrication. The most difficult issues to detect and verify are cited to be related to CDC (Clock Domain Crossings). These issues appear when signals in a circuit cross asynchronous clock boundaries without being synchronized. A single CDC issue, if not resolved, can render the whole chip useless. This problem gets enlarged as the number of clocks increases in the design space. In today’s SoC, there can be hundreds of asynchronous clocks driving different IP blocks and complex functions spread across the design.

Example of a Typical SoC Block Diagram

Today, a typical SoC can have billions of gates, multiple power / voltage domains driven by different clocks, while the design can operate in different modes of operations with particular portions of the design being active at different times. Such a design would need a verification methodology defined according to the design implementation and an intelligent solution for complete identification and verification of all CDC issues.

Traditional tools such as RTL simulators or static timing analyzers cannot precisely detect CDC issues. They often end up either under-reporting the real issues or over-reporting false violations, thus wasting a verification engineer’s time. A comprehensive approach is needed that can pin-point the real issues at lower levels and re-use the information at higher levels, thus optimizing the overall verification flow and improving the quality of verification.

Atrenta’sSpyGlass CDC uses a protocol independent analysis technology and provides a comprehensive methodology for CDC verification. Using this software a state-of-the-art structural analysis can be done which uses a suite of rule-sets to verify all kinds of structural CDC issues and avoid any kind of meta-stability. The protocol independent analysis identifies and filters out false negatives upfront, thus saving verification time. It can identify synchronizers such as FIFO and handshake protocols that are properly designed in a generic way. It can also identify signals which can synchronize crossings between clock domains and check if the crossings are functionally correct. The SpyGlass CDC solution also includes functional analysis that complements the structural analysis and ensures proper working of the circuit without any data loss, incoherency, or glitch. The functional checks are done either by using formal verification or simulation.

With these powerful CDC verification capabilities integrated into the SpyGlass Platform, designers have ultimate flexibility to do the verification in multiple ways – flat, hierarchical bottom-up or hierarchical top-down. This flexibility allows designers to handle different situations while designing an SoC which can vary in complexity and size from a few million to more than a billion gates. Again, all IP blocks may not be ready before integration; some of them may be coming from third parties without their functional views. The SoC designer can take appropriate action for the level of verification required for such IP and its interfaces within the SoC. Let’s take a look at the scenarios.

For small SoCs or smaller blocks of IP, the verification can be done in flat mode where the entire SoC is verified in a single run without missing any CDC bugs. The advantage in this case is ease of setup, as all clock modes and design constraints are available at the chip level.

Hierarchical bottom-up CDC verificationis highly scalable and can handle billion gate designs. However, in this case, blocks need to be setup and verified gradually as they are built. The SoC designer works with only CDC-clean blocks, verifies CDC at inter-block interfaces, and then creates an abstracted smart model for this block. In this approach, the verification quality can be ensured by maintaining completeness at each block and its higher level integration, along with coherency of constraints between each block and its top level. Use of these smart models can reduce the verification time and memory footprint by up to 10X.

In hierarchical top-down CDC verification, the constraints are created and driven from the top. This creates the possibility of having the SoC constraints refined early in the design cycle and the ownership of satisfying those constraints goes to the IP or block owners. The verification closure happens gradually as, and when, the blocks become ready. In the case of any third party IP for which the functional view may not be present, the SoC integrator needs to decide whether that IP should be fully verified or partially verified at the boundary.

The SpyGlass CDC verification flow also provides a closed loop between RTL and netlist level verification. At the RTL, substantial structural and functional analysis is done to find all CDC issues. In the netlist, insertion of clock gating, power optimization logic, and other changes may introduce new CDC issues. Therefore, it is mandatory to perform complete structural analysis again at the netlist level. The functional verification is done as required depending upon the fixes implemented during structural analysis. Depending upon the design hierarchy and complexity, it’s important that the verification methodology is defined upfront and that CDC verification be done for the complete SoC in the most optimal manner.

Read a detailed methodology description for CDC verification of billion gate SoCs in a whitepaper here at the Atrenta website. You will need to complete a short registration process in order to download these whitepapers. To get more insight into SpyGlass CDC verification methodology, you can attend an upcoming webinar with the following schedule:

Topic –Signoff Quality CDC Solution for Billion+ Gate Designs
Date/Time – March 19, 2015 4:00pm CET (8:00am PDT) and 10:00am PDT
Registration link –http://www.atrenta.com/events/?series=webinar-series-2015

The SpyGlass CDC verification flow is also tailored for FPGA designs. Atrenta provides a SpyGlass-FPGA-Kit that can be used in a XilinxFPGA-based design to make it Lint and CDC clean. Look for more details in another whitepaper “SpyGlass Lint/CDC Analysis for Xilinx FPGA” here.