At ARM TechCon I ran into Coby Hanoch who has just been appointed VP worldwide sales of a comany that I’d not previously heard of called Codasip. As the name implies they supply code, and ASIPs. Well, actually IP source code and ASIP tools. The company is based in Brno (pronounced pretty much like Bruno) in the Czech republic with a sales presense in US, EU, Israel, Japan, China and Korea. They have actually been working on technology in an incubator since 2006 but were spun out as a venture funded company in Q1 this year.
Coby was most recently at Jasper Design Automation where he ran worldwide sales. Of course Jasper was recently acquired by Cadence and so Coby was surplus to requirements.
ASIP stands for application specific instruction-set processor and they fill the gap between standard microprocessors such as ARM or MIPS, and writing RTL (or using HLS) to implement the functionality. You get close to the flexibility of a software-based solution with close to the performance of doing the RTL. ASIPs are typically used for doing very specific functions that require unique performance capabilities that a standard microprocessor cannot deliver, typically either ultra-low-power or else very high performance.
For example the “OK Google” engine above. A very low-power always on ASIP with very limited detection capabilities fronts a second ASIP with a full speech recognition engine to understand the request. Then depending on the request, other parts of the system are woken up (such as a high powered multi-core processor) to perform the tasks.
Codasip have a language, CodAL, for processor description. It supports all processor architectures such as RISC, CISC, DSP and VLIW. This is then run through Codasip Studio to generate all the views required to actually use the processor:
- Synthesizable RTL
- UVM testbench
- Compiler (using LLVM)
- Virtual platform
- And more…
IOT, wearable devices, automotive and medical products require many specific processors which provide best performance with minimal power consumption. Codasip’s profiler enables the designer to tailor the architecture and optimize the power-performance-area equation They also provide generic IP modules for RISC, DSP and VLIW which users can use to jumpstart the design, adding/removing/modifying them with total flexibility so they are optimal for their needs. They are focused on leveraging standard technologies such as LLVM, GNU, QEMU, etc., so the generated elements can be integrated with the rest of the customers environment.
As an example, look at Sobel edge detection with grayscale output. This takes in a color picture, finds all the edges and outputs a black and white version with all the edges highlighted. By introducing a 128-bit SIMD extension they immediately get a 4X speedup compared to optimization done entirely at the sotware level.
Once the architect defines the Instruction Accurate model, the SW/Firmware team can immediately compile their code, run it on the emulator, and debug it, even before the HW guys developed the microarchitecture and have any RTL. The architects can profile the model and add/remove instructions/registers/memory elements to optimize the architecture. This means that software development and SoC development can proceed in parallel, pulling in the design schedule significantly.
The Codasip website is here.