Digital Implementation and AI at #62DAC

My first panel discussion at DAC 2025 was all about using AI for digital implementation, as Siemens has a digital implementation tool called Aprisa  which has been augmented with AI to produce better results, faster. Panelists were from Samsung, Broadcom, MaxLinear, AWS and Siemens. In the past it could take an SoC design team 10 to 12 weeks to reach timing closure on a block, but now it can be done in 1-2 weeks with Aprisa AI

Using Aprisa AI has also improved the compute time efficiency by 3X, providing a 10% PPA improvement while beating the old way of writing expert scripts. Here’s my take on  the interactive panel discussion.

AI used in EDA tool flows at DAC in 2025 was quite a popular theme, and it helps to meet the challenges of complex ASICs that have multiple power domains, 2.5D and 3D chip designs and even in planning before implementation. The cost to manufacturing designs has doubled just in the past two nodes, so there’s a need to be more efficient and have chips consume less energy.

One technique to speed up verification is using a chatbot to create test benches and suites, as natural language queries are quicker than manually writing UVM. The engineering shortage is impacting SoC designs and even training new engineers takes valuable resources, so AI is helping out by shortening the learning curve with EDA tools and make experienced engineers more productive.

AI is being used to make early tradeoff explorations possible, resulting in improvements in PPAT. A new hire can be trained using AI with natural language in about one month, instead of the old way taking six months. Even variants of a design can be done more quickly with AI in the flow with fewer engineers than before.

Before AI usage in EDA flows design teams couldn’t take on all the projects that they wanted to, because of the lack of engineering resources, and with 3nm chip designs costing $300M the pressure is on to get first silicon working. Previous design cycles of 12-18 months are now possible to compress into 6-9 month cycles, fueled by AI-based tools.

Our semiconductor industry has a market size of $650 billion today, projected to reach $1T by 2030, when we expect to see systems with 1 trillion transistors, aided by AI taking on many of the routine engineering tasks like optimizing EDA tool runs.

Agents are poised to enter EDA flows, further improving efficiency and productivity of design and verification teams. Agents will do optimizations and agentic AI will help to solve some complex problems, finding new solutions.  These optimizations need to be accurate enough to be relied upon. Humans will still focus on the architectural tradeoffs for a system.

EDA design and verification in the cloud has taken off in the past three years, as . We can expect to see AI agents doing placement and routing, maybe even improve timing closure tasks. Verification agents can help today by analyzing and even removing human-induced errors.

AI usage is driven both from the top-down and bottom-up in organizations, as managers and engineers discover and benefit from AI efficiencies and improvements. Learning how to prompt an LLM for best results is a new engineering skill. Reports and emails are benefiting from the use of ChatGPT.

Larger companies that train their own LLM will have an advantage over smaller companies, simply because their models are larger and smarter. We still need human experts to validate all AI results for correctness. EDA companies that have created LLMs report rapid improvements in the percentage of correct answers.

Reaching power goals is possible with AI, and the Aprisa tool from Siemens is showing 6-13% improvements. Engineers don’t have to be Aprisa tool experts to get the best results, as AI decides which tool setting combinations produce the best results.

Bigger, more complex SoC projects see more benefit from AI implementation tools, as it chooses the optimal tool settings based on machine learning. Full-custom IC flows are also reporting benefits from AI-based flows. Aprisa is working on how to do custom clock tree generation through a natural language interface, and there’s currently a cockpit to invoke natural language. Aprisa AI results are showing 10X productivity, 10% better PPA, with up to a 3X improvement in compute time efficiency.

Summary

Full Agentic flows are the long-term goal for EDA tools and AI today is helping improve full-custom IC design and big digital design implementation. Engineers need to adapt to the use of AI in their EDA tool flows, learning the best prompts. With new efficiencies it is possible to have fewer engineers that are more productive than their predecessors. EDA customers want the option to use their own LLMs or change LLMs as they see fit in their tool flows.

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