Aniah and Electrical Rule Checking (ERC) #61DAC

Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working at STMicroelectronics and started Aniah for Electrical Rules Checking (ERC) in 2019. Their tool is called OneCheck, and it operates on transistor-level netlists like CDL formats, then reports on several issues like: domain crossings, floating gates, electrical overstress, diode leakage, conditional HiZ nodes, ESD, and missing level shifters between voltage domains.

The OneCheck tool has a UI that enables an IC designer to load a netlist and get analysis results quickly. I heard that the Calibre PERC tool required 2 days to load and analyze a customer design, but OneCheck was much quicker, taking only few minutes. Vincent showed me a live demo running on a laptop where the design had 19 million transistors, and it was for a camera sensor chip. OneCheck detected all the different power regions, then completed all analysis in under 5 seconds. Initial results reported 2,257 missing level shifters in the netlist, and the errors can be clustered by priority then root cause. In general, there are four categories of errors:

• CMOS logic
• Mixed-signal topologies
• Complex propagation paths
• False errors

The root cause of the 2,257 errors was a CMOS inverter, under a specific power scenario, so clicking on this error in the GUI automatically created a schematic showing the propagation path. Engineers can continue to navigate forward or backward through the auto-generated schematic to understand the context of each issue reported. Vincent then cross-probed with Cadence Virtuoso Schematic Editor to better see the issue identified.

Inside of the OneCheck GUI you can use it in Standard or Advanced mode, where Advanced mode allows one to cluster errors by property, like voltage, then filtering by cell names. Users can make all circuit properties visible, making it easier to pinpoint and fix each issue found. There are many pre-packaged checked for all types of design on processes from .25um BCD to 3 nm CMOS, and engineers can develop and code their own unique checks to identify trouble topologies. Most checks take about 5-10 lines of code. Stay tuned for using Python functions to write your own checks, it’s coming soon.

Analyzing all electrical errors for IP blocks, sub-systems and SoC at the top-level really require an automated approach, because you cannot have circuit designers manually look at netlists to enforce best practices. If your electrical rule checking tool is producing too many false errors, then you’re wasting valuable time. The secret sauce with Aniah is the use of formal technology during analysis of the transistor-level netlists, thus reducing false errors and speeding the identification of root causes.

Aniah has attended several events recently: CadenceLIVE Taiwan, DVCon, DATE 2024. You can learn more at their next webinar, September 26th, 9:00AM – 10:00AM PDT, hosted by SemiWiki. Distribution partners include Saphirus in the US, Kaviaz Technology in Taiwan, and Lomicro in China, Micon Global in Europe and Israel.

Summary

My engineering background is transistor-level circuit design, so viewing what Aniah has done with OneCheck was quite encouraging. Quickly identifying circuit design issues with a minimum of false errors by using formal techniques looks very promising and improves first silicon success. The speed of OneCheck running on a laptop was also impressively fast, while most EDA vendors don’t even run their tools live at DAC any more.

Related Blogs

• Electrical Rule Checking and Exhaustive Classification of Errors
• CEO Interview: Vincent Bligny of Aniah