Are you Aware about Risks Related to Soft Errors?

Soft errors change stored data and cause temporal malfunctions in electronic systems. This mainly occurs when radiation particles collide with semiconductor devices. Soft errors are a concern in all environments, whether in the atmosphere, in space, or on the ground.

Soft errors are critical in high-reliability applications such as automotive, aerospace, medical, and high-performance computing. A Single-Event Upset (SEU) or Multi Bit Upset (MBU) can cause data corruption or software crashes that can have severe consequences for these applications.

For example, in 2003, soft errors in voting machines used in Belgium’s elections counted 4,096 more votes than voters (Ref1). Soft Error problems have been manifesting themselves for decades (Ref2) and the problems will continue to increase as chips become larger, increasing in density and functionality.

IROC solutions for Soft Error assessment in your design:

IROC Technologies is specialized in providing best-in-class EDA solutions and test/consulting services for soft error analysis and mitigation. With our expertise and know-how, we help our customer to get more confidence in their chips against radiation effects.

• TFIT®: predicts FIT rate at the cell level and provides help for optimal hardening solutions
• SoCFIT®: analyzes propagation of the soft errors at SoC level and provides mitigation strategies
• SERTEST: provides radiation particle test in international world-class laboratories
• SERPRO: provides consulting for SER management and mitigation for complex systems

IROC helps customers throughout all phases of chip design and development. Using IROC EDA solutions in a standard EDA flow early in the design cycle reduces costs and saves time while enhancing the reliability of your chip. IROC design consulting and radiation testing can help to optimize and verify your designs for optimal SER.

Customers & Partners:

More than 130 companies, including over 50% of the top semiconductor companies have benefited from IROC’s deep experience in radiation effects. Over a 23 year history, IROC has nurtured partnerships and long-term relationships with major foundries such as TSMC, Samsung, Global Foundries, the European Union, and CEA. Foundries, in particular, have used IROC EDA products to enhance PDKs to help reduce soft error problems in their customers’ designs.

Who benefits from IROC solutions?

• TFIT®
  • cell developers such as foundries, IP vendors, and custom cell designers
  • reliability engineers looking for raw soft error rates of basic cells in their chip design
• SoCFIT®
  • reliability engineers targeting chip reliability problems caused by radiation
  • designers who wish to analyze and mitigate propagation of soft errors and reduce the Soft Error Rate (SER) at SoC-level
• SERTEST/SERPRO:
  • chip and system providers who want to verify the reliability of their chip
  • chip and system providers who seek expert advice to optimize the radiation related reliability of their designs

Example of IROC customers’ use cases:

Automotive: TFIT was used to harden Flip-Flops. TFIT provided analysis and suggestions for schematic and layout changes. The customer was able to achieve clean triple modular redundancy implementation and discovered a potential weakness related to angular impacts.

Aerospace: SERPRO team is working actively with the European Space Agency (ESA), recently completing a project in 16nm FinFET. Additional projects with even more advanced nodes are in the pipeline.

Medical: SERTEST team successfully analyzed and identified the root cause of a critical issue in a pacemaker application, resulting in the implementation of improved qualification and testing procedures for the customer.

HPC: Customer was able to lower their Failure in Time (FIT) Rate 7X by using SoCFIT on several, complex digital circuits including 40Mbit SRAM, 1.7M FF, 13M-Combo Gates.

Shi-Jie WEN, Distinguished Engineer, Advanced Silicon Technologist at CISCO Systems said: “Cisco benchmarked TFIT with results of tests on silicon for several designs and other tools. The correlation between the simulation results and test is impressive for this particular process node – TSMC 40nm. Cisco is committed to continue our correlation work with TFIT on the other Si technology nodes. TFIT stands as one of the best commercially available simulation tool offered to the industry for soft error simulation.”

If you would like to know more about IROC Technologies and our offerings, please do not hesitate to contact info@iroctech.com or visit www.iroctech.com.

Ref 1: https://en.wikipedia.org/wiki/Electronic_voting_in_Belgium

Ref 2: https://www.computerworld.com/article/2584471/q-a–mcnealy-defends-sun-reliability–personal-privacy-views.html

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