Bespoke Silicon Requires Bespoke EDA

When I first heard the term ‘bespoke silicon,’ I had to get my dictionary out. Well versed in the silicon domain, I did not know what bespoke meant. It turns out to be a rather old-fashioned term for tailor made and seems to be very much British English. The word dates from 1583 and is the past participle of bespeak, according to the Oxford English Dictionary. American English by contrast more commonly uses the word custom. By now, custom silicon has been rebranded to bespoke silicon.

All the same, with plenty of attention in the industry [1], academia [2] and at conferences [3], I am now convinced bespoke silicon is here to stay.

But it seems that most participants in the bespoke silicon conversations miss out on one important aspect. Bespoke silicon requires bespoke EDA (electronic design automation), because one size does not fit all in EDA either. When I say bespoke EDA, I’m not talking about heavy duty work horses like place-and-route tools, static timing analyzers, or HDL simulators. These are fine-tuned to the hilt and support wide varieties of design styles. However, in the first steps of design creation, at the register transfer level (RTL), there are many side steps that can be made to improve the quality of a bespoken silicon design.

An interesting aspect is that it is difficult to provide tangible examples of bespoke EDA. System design houses that we interact with do not tell us what kind of bespoke EDA they are creating. After all, they do not want that information shared with their competitors, although one can easily guess the domains that get the most attention. Low power design tricks, design for test circuitry, intellectual property (IP) customization, and debug functionality quickly come to mind.

Standardization places an important role in bespoke EDA. Without the likes of SystemVerilog, VHDL, UVM, UPF, and encryption standards, it would be difficult to move design content around different EDA tools.

Traditionally, EDA tools are written in C and C++ but those are not languages of choice for semiconductor design teams implementing bespoke EDA. Python, with its vast infrastructure and freely available open source packages, seems to be the front-runner here.

Another advantage that bespoke EDA can bring is the equal treatment of SystemVerilog and VHDL. Rather than dealing with different APIs to obtain, for example, all output ports in a VHDL entity or SystemVerilog module (and ending up with two scripts at the end), it is a lot more productive to have a single API aptly named all_outputs(object)and be done with it. Bespoke EDA’s building blocks will take care of it under the hood.

As I mentioned before, hard-core EDA tools are not going to be replaced by home-grown bespoke EDA applications. But don’t be surprised if real innovation will come from inside semiconductor design organizations that focus significant efforts on their in-house bespoke EDA applications.

About Verific Design Automation

Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

[1] https://www.ansys.com/blog/behold-the-dawning-of-the-era-of-bespoke-silicon

[2] https://www.bsg.ai/

[3] https://www.linkedin.com/pulse/designcon-bespoke-silicon-paul-mclella

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