56th DAC Empyrean Stepping Up ALPS with GPU Implementation

As a testament to the technology advances developed and implemented into Empyrean ALPS™ by the engineering team, the product has seen a steady growth in the adoption by users. In addition, hearing directly from the users at DAC 2018 turned out to be an all-around success for the product as well as the product team to see ALPS beating other established parallel SPICE simulators in performance while maintaining the same accuracy. When good work is recognized, engineering motivation shoots up and greater outcomes begin to happen. You can see that in the form of GPU-accelerated ALPS at the 56^th DAC. The recent announcement of Empyrean ALPS being voted by users at DAC 2018 as “Best of 2018 DAC” in SPICE simulation is yet another recognition of the product and the product team. The outcome of all the above is the introduction of a GPU-accelerated ALPS at the upcoming 56^th DAC at Las Vegas, Nevada.

SPICE Simulation Challenges

In any typical SPICE simulation run, close to 90% of the time is spent on two operations: Device model evaluation and matrix solving. Empyrean’s engineering team came up with a novel algorithm, the Smart Matrix Solver (SMS) to address matrix solving. A multi-threaded, CPU-based architecture and the Smart Matrix Solver empowered ALPS to run not only faster, but also maintain the same accuracy with SPICE. The speedups were to the tune of 3X to 8X over other simulators and without the need for accuracy trade-off using model simplification of RC reduction techniques on analog and mixed-signal designs, especially with post-layout simulations runs where the parasitics add up to tens of millions of elements, impacting performance and accuracy. Click here for user feedback on ALPS. Join us at the 56^th DAC in Las Vegas, Nevada at the Empyrean booth #651 to learn about Empyrean ALPS.

Stepping Up with GPU-Based Architecture

The product success further motivated the engineering team at Empyrean which had been actively working on a GPU-based implementation. With a GPU-based architecture, they were able to cleverly direct and massively parallelize the two time-consuming operations, device model evaluation and matrix solving to the GPUs with 1000s of cores, while keeping rest of the simulation operations on the CPU. Working closely with some key customers, the most common hardware, NVIDIA’s Tesla V100 was selected as the platform to use. NVIDIA’s CUDA™ solver that came with V100 was fast but not fast enough for SPICE runs. The team enhanced the Smart Matrix Solver by optimizing it for GPUs to achieve greater simulation performance while keeping accuracy. Empyrean will be talking to early customers for this product, called Empyrean ALPS-GT™ at the suite at DAC.

AI -Powered IP Timing Arc Prediction

Further strengthening its position in the AMS design, Empyrean will be showcasing a new AI -powered timing arc prediction especially for analog and mixed signal IP and library circuits. This is a capability that Empyrean developed by working closely with a few key customers. A joint paper with NVIDIA is being presented on this at the Designer Track session at DAC 56 (Paper ID:268-WC54).

Timing arc prediction for an analog or AMS circuit is relatively difficult, and with the AMS content continuously increasing in SoCs, the need for accurate prediction is critically important and can often lead to costly silicon failures. Please stop by the Empyrean booth (#651) to learn about this capability in Empyrean Qualib-AI™ product and how it is being applied to designs.

The most recent blog on SemiWiki by Daniel Payne goes into more details on the GPU-accelerated SPICE and the AI-powered Qualib.

Better SoC Design, Debug and Analysis

Empyrean’s claim to fame in the SoC market was with Empyrean X-Top™, a comprehensive timing eco analysis and fixing capability, which was first adopted by Marvell, and later making it a required sign-off tool in their flow. X-Top is an ultra large capacity placement and routing aware timing eco engine with automated and interactive eco capabilities. Today’s complex multi-voltage domain designs with simultaneous multi-mode multi-corner (MMMC) optimization are ideal candidates for this tool. Stop by Empyrean’s booth at DAC to check out X-Top and how it is in the tape-out flow of many companies.

Empyrean’s ClockExplorer™ is another valuable solution for diagnosis and analysis of clock circuits in today’s designs with complex clock domains. Its powerful visual diagnosis capabilities provide the back-end implementation teams the ability to easily visualize clock networks and implement it as intended by the front-end design team, thereby reducing unnecessary silicon iterations. Stop by the Empyrean booth to check out ClockExplorer.

Skipper™ has been a great add-on to the SoC design flow at many companies to analyze very large pre and post-silicon layout database for anything from DRC/LVS debug to failure analysis. Its very fast layout bring-up, IP merging and post-silicon FIB processing along with powerful diagnosis and analysis capabilities make it an attractive add-on to many SoC design flows. Skipper was also recognized by users at DAC 2018 as “Best of 2018 DAC.” Click here for the user feedback on Skipper. Stop by the Empyrean booth to check out Skipper.

About Empyrean Software

Founded in 2009, Empyrean Software is an Electronic Design Automation (EDA) and intellectual property (IP) technology leader in delivering fast and true physically aware, design closure and optimization solutions for timing, clock and power of system on chip (SoCs). The company also offers a high-performance accurate circuit simulator and is an analog IP and fast SerDes IP provider. For details, go to Empyrean Software.