Computational Lithography, Scaling’s Best Friend

By Joseph Sawicki, Vice President & General Manager, Design to Silicon Division

It is one of the more amazing stories in the continued march of Moore’s Law over the past four nodes. Previously scaling was enabled solely though changes in the physical domain, whether through decreasing the wavelength of light, increasing the numerical aperture, or producing chemically amplified resists. Starting at 180 nm software has become a critical driver of scaling. The discipline of Computational Lithography (CL) combines software architecture and high performance computing, with modeling of the scanner, resist and etch process, into a system that can correct for the deficiencies of the physical domain by correcting the shapes on the mask.

As a measure of how far this discipline has come, it is interesting to look at the processing necessary to implement this correction in an advanced node. Current estimates for the 28nm node show the need for about ten teraflops of sustained performance for about 24 hours in order to correct a single critical layer. To put this in perspective, the top computer on the world TOP500 Supercomputer Sites list (www.top500.org) did not hit this level until 2002! Key to this innovation was work in the area of high performance computing to allow standard computers connected through an Ethernet backplane to be combined effectively to solve this problem. What is particularly stunning is that we can achieve this performance level using just 800 CPU cores.

Continued scaling in the absence of EUV will require continued innovation in CL. Techniques for managing double patterning, double dipole lithography, model-based Sub-Resolution Assist Features and optimized illuminators are all in late development or deployment stages today.

The most aggressive development efforts in CL are in the area of Source Mask Optimization. Here the concept is to go beyond modifications in the mask alone, instead co-optimizing the illuminator and mask on a per-design basis. Doing so has the potential to significantly increase the process window available with a 193nm scanner, and could be used to extend optical lithography to the 16nm node.

EUV has been tomorrow’s technology for quite some time now. First thought of as a replacement for 193nm at the 90nm node, its deployment remains a controversial topic. Though there are still some supporters who position EUV as the solution for the 22/20 node, many now believe that continued development issues will delay EUV until the 16/14 nanometer timeframe.

While some commentators also see EUV as a replacement for CL, the delay in EUV’s development ensures that this is not the case. Just looking at K1 (from Rayleigh’s equation: Resolution = K1*λ/NA) will help to understand why this impression is false. Back at the 90nm node, K1 was approximately 0.55 for critical layers and model-based OPC was a necessity. At the 16nm node, K1 for EUV on a critical layer will be even less at 0.47, assuming an NA of 0.25, indicating the continued necessity of CL.

However, K1 alone does not tell the whole story. EUV also has distortions driven by two long range effects: flare and mask shadowing. Capable of driving a total variability across the reticle field of greater than 10nm, these effects will need compensation in order to produce the CD uniformity necessary for successful scaling.

“The End Of,” makes for a very popular headline, and we’ve seen any number of these headlines spoken about semiconductor manufacturing over the years. I’m old enough to remember when it was clear to all that sub-micron manufacturing would never be done. What is clear is that the economics of scaling is a very powerful driver for innovation, affecting the behavior of thousands of engineers and driving significant corporate investment. At some point “The End Of” will come, after all it is difficult to imagine a gate smaller than one atom across. Until then, continued developments in Computational Lithography will help enable scaling for a number of nodes to come.