How Do You Extract 3D IC Structures?

The press has been buzzing about 3D everything for the past few years, so when it comes to IC design it’s a fair question to ask how would you actually extract 3D IC structures for use by analysis tools like a circuit simulator. I read a white paper by Christen Decoin and Vassilis Kourkoulos of Mentor Graphics this week and became intrigued by some new extraction technology coming our way. Back in May 2012 Mentor joined STMicroelectronics and other companies as part of the Grenoble Institute of Technological Research (IRT). This joint work is the result of that collaboration.
TSV Structure
Consider a through-silicon via (TSV) structure used in creating 3D ICs:

Model-based Approach
An analysis approach can be applied to 3D IC structures like the TSV with a flow of: design the TSV, use a field solver, create an abstracted reference model, simulate with the reference model. Such an approach with abstracted models makes some simplifying assumptions which can lead to inaccuracies, consider what happens if you don’t model coupling effects between TSV structures:

L at low frequencies has little affect on the Amplitude os S-parameter S12 shown on the left chart, however the chart on the right shows that inductance does need to be extracted for accurate TSV analysis.

Field Solver Approach
The new technology coming from Mentor Graphics will solve Maxwell’s equations directly and provide both:

• Field solver accuracy
• Acceptable run times

The new flow will accept the 3D IC layout as a GDS II file and a fule file, run the quasis-electrostatic field solver creating capacitance and conductance values, run a quasi-magneto-static field solver creating inductance and resistance value, optimize and create an RLC netlist.

Capacitance
For capacitance accuracy Mentor choose the method of moments (MoM) approach and then tuned it for speed. Because a field solver is being used the designer can layout any TSV structure or geometry. Passivity is enforced so your circuit simulator will converge when running the extracted netlist and the flow is automated, and much simpler to use than a TCAD tool.

The first TSV structure shown in this blog was run through the field solver in about 900 msec. Early results show an extraction speed of 4,000 structures per hour. By using multi-threading you will be able to extract 100,000+ 3D structures in an overnight run.

The gold standard for accuracy is Ansoft’s HFSS (High Frequency Structure Simulator), so let’s see how the accuracy compares on a typical TSV structure:

The blue and red squares show HFSS reference values while the lines show Mentor’s results with extracted values, and the generated netlist values are shown as circles. There’s excellent correlation between HFSS and the new approach by Mentor.

Inductance
The new Mentor approach is using a loop impedance formulation to extract both inductance and resistance of TSV structures. Comparing the accuracy of this approach versus TCAD reference values shows good correlation:

With Mentor’s new approach the amplitude accuracy is within 4.5% and phase accuracy within 1.25% of TCAD results across the frequency range selected.

Summary
Mentor has a new field-solver based approach to 3D IC extraction that is both accurate and fast for TSV structures. Stay tuned for an actual product announcement in early 2013. This approach is complimentary to the existing Calibre xACT 3D tool in use today.

Related blogs on field solvers:

• Who Needs a 3D Field Solver for IC Design?
• An Affordable 3D Field Solver at DAC
• Memory Cell Characterization with a Fast 3D Field Solver
• A New Hierarchical 3D Field Solver
• Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop
• QuickCap for IC Extraction at DAC 2011
• 3D Transistors and IC Extraction Tools