Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.
Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)
ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun Research Labs for EDA, Ph.D in Magnetics and Computer Science).
Ravi Ravikumar joined ICScape just two months ago, and we had worked together back at Viewlogic in the 90’s.
Their tools address issues like Clock and Timing closure. The old way of using STA (Prime Time), P&R (Cadence), caused you to iterate maybe 10 or 12 times to reach timing and clock closure.
A new way with IC Scape tools is to work off of timing graph of PrimeTime, use a built-in layout engine to understand the physical topology, and now iterations are about 3 to 4 instead. They have sold Clock Explorer to Marvel in 2007, an early customer.
Clock Explorer – SOC clock tree tool to drive a CTS to improve the quality of the design across multiple clock domains, could be 100’s of clock domains. Generate clock constraints, drive the CTS tools (Synopsys, Cadence). See sales for prices. Customer: Marvel (many designs: Video, networking, HD)
Timing Explorer – Back end P&R flow has challenge to close the timing manually. Starting at 45nm the physical layout must be considered during timing however PrimeTime doesn’t understand or take into account physical layout issues. Multiple scenarios – 30 to 80 scenarios for a 28nm design, how do you use an existing timing flow for this? Our tool solves this through a multi-threaded approach on designs up to 100million instances. Customer: Marvel, High Silicon (Largest IC design company in China). Reduces timing closure by 1/2 (typically it took them 10 iterations before at 3 days per iteration, now it takes just 2 weeks to converge). About 45 times faster than a PrimeTime only flow, because it is the Golden sign-off STA tool.
Physically-aware, multi-corner, multi-mode ECO timing closure tool.
Funding was received through a merger with HES, and so they now have some $28M.
Merged with HES (Emperian Software) in 2011, over 20 years in EDA for the China market. Complete tools for AMS: Schematic (Aether for OA, PDK, API) as 6th generation. Aether LE for Layout. Schematic Driven Layout. SPICE simulator is Aeolus (between HSPICE and Fast SPICE), with a capacity of 10 million devices. Aeolus is parallel architecture (8 cores is a 7X speed up, but about 4X is typical).
Chinese foundries have used Aeolus (CSMC – Chinese foundry).
DRC/LVS – Argus tool name, uses its own rule deck. IC Scape will write rules for any process. An alternative to using Calibre that is lower cost.
RC Explorer – Automate the full custom IC design cycle by doing an early layout simulation to do early route estimates (gridded and gridless router) even when design is early and incomplete. Some analysis of extraction between any two points to find paths and simulate RC values. Also works with any external RC extraction tool using DSPF or SPEF interconnect file, all OA based. Support Virtuoso 5.1 and 6.1, even Laker tools.
How do you sell these tools? Pieces or the entire suite of tools.
Skipper – high performance and high capacity chip finishing, handles huge layout database with 100GB GDS II or OASIS formats. Layout viewing and layout editing capabilities with finishing like IP merge. Output can be GDS II. FlashLVL – layout versus layout comparison tool, fastest in the world about 10X faster than any other commercial tool. You can buy just FlashLVL, Skipper or suites.
250 people in the company, mostly from China.
Expanding in Japan, Korea and Taiwan.
Over 100 tape outs so far.
Just started marketing in the USA.
Did 350 live demos of products this week at DAC.
The software runs on Linux (not windows).
Licensing: FlexLM
Every 3 months for release or service packs.
MPS (Monolithic Power Systems) – one of top three power management companies.
Summary
ICScape is just starting their awareness building campaign in the US by offering point tools to speed up clock and timing closure of digital designs, plus IC tools for transistor-level design, simulation, layout and extraction.
Build a 100% Python-based Design environment for Large SoC Designs