Collaboration Required to Maximize ASIC Chiplet Value

It is a well-known fact that chiplets provide several advantages over traditional monolithic chips. Despite these benefits, the transition to a chiplet-based design paradigm presents challenges that need coordinated efforts across the industry. In essence, collaborative efforts among various players involved are not just a nicety, but rather a hard requirement to realize the full benefits. And an ASIC provider can optimize the benefits even further by customizing the various chiplet components of a design.

I recently interviewed Erez Shaizaf, the CTO of Alchip Technologies, Limited, to gain deeper insights into how the combination of the chiplet-paradigm and an ASIC approach can maximize the benefits to be derived from chiplets. Alchip is a leading provider of silicon design and production services for merchant silicon and system companies developing complex and high-volume ASICs and SoCs. Here are the excerpts from that interview.

The Importance of Collaboration in Chiplet-Based Design

In a fast-paced industry where new tape-outs occur every 12 to 18 months, having the right technology is only part of the solution. Efficient execution is equally critical. Chiplet-based designs and advanced packaging technologies are inherently complex, requiring a multi-disciplinary approach to achieve peak performance and maximize financial returns. Extensive collaboration across the ASIC value chain ensures seamless integration from the architecture phase to design, all the way to mass production ramp-up.

Alchip’s Collaborative Efforts

Alchip collaborates closely with IP vendors, EDA providers, foundries, and assembly partners to ensure seamless integration of cutting-edge technologies into advanced packaging designs. This includes managing high-bandwidth memory and numerous UCIe lanes for high die-to-die bandwidth, along with 224G/PCIe multi-lane architectures to support both scale-up and scale-out needs. By partnering with EDA vendors across all stages of design, from RTL to GDS, and through package design and sign-off phases, Alchip streamlines design processes, optimizing them for rapid production and reduced time to market.

In addition to its work with EDA vendors, Alchip collaborates with foundries such as TSMC to ensure compatibility with advanced process nodes and packaging types. This holistic approach extends to assembly and testing partners to validate designs and accelerate the transition from tape-out to mass production. Through optimized package and interposer multi-die floor planning and careful supply chain management, Alchip enables high-volume production efficiently, meeting diverse customer needs while minimizing risk and ensuring smooth transitions from design to mass production within the shortest possible time.

Critical Role of ASIC Providers in the Chiplet Ecosystem

Despite the buzz surrounding chiplets, Alchip challenges the notion of a “chiplet market.” In reality, chiplet development remains largely captive, with an estimated 90% of chiplet development occurring internally within organizations (with the exception of high-bandwidth memory). Each customer has unique performance demands — spanning functionality, bandwidth, process node, and package type — that make a generalized chiplet market hard to foresee.

However, Alchip has taken proactive steps to address these challenges by developing the Soft Chiplet approach, a modular, front-end ready design that allows for rapid tape-out. This modular approach covers various aspects of chiplet design — including verification, firmware, delivery, documentation, and ready-to-harden flow. The Soft Chiplet is an embodiment of Alchip’s collaborative philosophy, allowing flexibility for different customer requirements while speeding up the tape-out process.

Handling Design Complexity in Multi-Die Systems

Designing multi-die systems and chiplet-based architectures introduce significant complexity. Alchip navigates this challenge by leveraging its talented engineering team, who continuously seek out the best new solutions. The Alchip team drives the ecosystem to innovate and collaborate in meeting customer demands.

Additionally, Alchip’s R&D efforts ensure that the company is always prepared for “the next node” — whether it’s 5nm, 3nm, or beyond. This approach positions the company to provide customers with the most cutting-edge technologies when they need them, ensuring faster tape-outs and more efficient designs.

Packaging Solutions for Chiplet Integration

Alchip supports all TSMC advanced packaging types, as well as certain advanced OSAT packaging solutions, to ensure optimal compatibility with diverse chiplet integration needs. These packaging solutions are critical for achieving the best possible performance and power efficiency in chiplet-based designs. Through its internal R&D efforts, Alchip continuously develops packaging solutions that address the evolving demands of its customers, ensuring high performance and efficient integration across a wide range of applications.

Success Stories

Alchip is a trusted partner for cloud service providers, merchant silicon companies, and innovative start-ups, each of whom has unique design and performance requirements. The company’s ability to tailor ASIC solutions to these varying needs underlines its value as a collaborative partner. However, due to the custom nature of these designs, specific case studies remain confidential.

Summary

Alchip is dedicated to pushing the boundaries of the chiplet ecosystem through collaboration and continuous technological progress. It is actively advancing its Soft Chiplet initiative, with a working prototype expected by the end of this year. This development is part of a broader roadmap aimed at building a flexible and collaborative ecosystem for chiplet-based systems. The company plans to reveal more about its advancements in chiplet technology at upcoming conferences.

To learn more, visit www.alchip.com

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