WP_Term Object
(
    [term_id] => 16377
    [name] => OpenFive
    [slug] => openfive
    [term_group] => 0
    [term_taxonomy_id] => 16377
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 13
    [filter] => raw
    [cat_ID] => 16377
    [category_count] => 13
    [category_description] => 
    [cat_name] => OpenFive
    [category_nicename] => openfive
    [category_parent] => 386
    [is_post] => 
)
            
OpenFive PNG 1
WP_Term Object
(
    [term_id] => 16377
    [name] => OpenFive
    [slug] => openfive
    [term_group] => 0
    [term_taxonomy_id] => 16377
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 13
    [filter] => raw
    [cat_ID] => 16377
    [category_count] => 13
    [category_description] => 
    [cat_name] => OpenFive
    [category_nicename] => openfive
    [category_parent] => 386
    [is_post] => 
)

Chiplets at the Design Automation Conference with OpenFive

Chiplets at the Design Automation Conference with OpenFive
by Daniel Nenni on 08-02-2022 at 10:00 am

OpenFive Chiplet 59DAC

SemiWiki has been tracking the popularity of chiplets for two years now so it was not surprising to see that they played a key role at DAC. The other trend we foresaw was that the ASIC companies would be early chiplet adopters and that has proven true. One of the more vocal proponents of chiplets at DAC#59 was OpenFive, a 17+ year spec-to-silicon… Read More


OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium

OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
by Kalar Rajendiran on 07-19-2022 at 10:00 am

Snapshot of Contributing Members of UCIe

Universal Chiplet Interconnect Express (UCIe) is an open specification that defines the interconnect between chiplets within a package. The objective is to enable an open chiplet ecosystem. Although the initial specification for UCIe was developed by Intel, a consortium was announced in March with Intel, AMD, Arm, Google,… Read More


IP Subsystems and Chiplets for Edge and AI Accelerators

IP Subsystems and Chiplets for Edge and AI Accelerators
by Daniel Payne on 05-02-2022 at 10:00 am

Scalable Chiplet Platform min

From a business viewpoint we often read in the technical press about the virtues of applying AI, and in the early days most of the AI model building was done in the cloud, because of the high computation requirements, yet there’s a developing trend now to use AI accelerators at the Edge. The other mega-trend in the past decade… Read More


A 2021 Summary of OpenFive

A 2021 Summary of OpenFive
by Kalar Rajendiran on 02-01-2022 at 10:00 am

Key Features of the Edge AI Vision Platform

Building a better mousetrap plays a key role in achieving market success in any industry. Of course, building one requires differentiating the product from the others already in the market. A differentiated product can even lead to creating demand for new products in adjacent markets. All of this is great but how do you implement… Read More


Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads

Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads
by Kalar Rajendiran on 05-17-2021 at 10:00 am

SuperCharge ML Performance

During the week of April 19th, Linley Group held its Spring Processor Conference 2021. The Linley Group has a reputation for convening excellent conferences. And this year’s spring conference was no exception. There were a number of very informative talks from various companies updating the audience on the latest research and… Read More


Die-to-Die Interface PHY and Controller Subsystem for Next Generation Chiplets

Die-to-Die Interface PHY and Controller Subsystem for Next Generation Chiplets
by Kalar Rajendiran on 04-19-2021 at 10:00 am

Comparison of D2D PHY and XSR SerDes OpenFive

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been… Read More


Enabling Edge AI Vision with RISC-V and a Silicon Platform

Enabling Edge AI Vision with RISC-V and a Silicon Platform
by Tom Simon on 03-15-2021 at 10:00 am

AI Chipset Market

AI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling facts in their recent paper titled “Enabling AI Vision at the Edge.” AI vision is being deployed in many applications, such as autonomous vehicles, smart cities, … Read More


CEO Interview: Dr. Shafy Eltoukhy of OpenFive 

CEO Interview: Dr. Shafy Eltoukhy of OpenFive 
by Daniel Nenni on 03-05-2021 at 6:00 am

Shafy Eltoukhy

Dr. Shafy Eltoukhy has over 35 years of experience in the semiconductor industry. He served as VP and BU manager of the Analog Mixed Signal Group at Microsemi. He was the VP of Operations and Technology Development at Open-Silicon. He was the VP of Technology at Lightspeed Semiconductor where he joined the founding team that invented… Read More


WEBINAR: Differentiated Edge AI with OpenFive and CEVA

WEBINAR: Differentiated Edge AI with OpenFive and CEVA
by Bernard Murphy on 11-10-2020 at 6:00 am

Enablin AI Vision at the edge min

OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir… Read More


Open-Silicon SiFive and Customizable Configurable IP Subsystems

Open-Silicon SiFive and Customizable Configurable IP Subsystems
by Daniel Nenni on 02-01-2019 at 12:00 pm

After 8 SemiWiki years, 4,386 published blogs, and more than 25 million blog views, I can tell you that IP is the most read semiconductor topic, absolutely, and that trend continues. Another correlating trend (from IP Nest) is the semiconductor IP revenue increase in relation to the semiconductor market (minus memory) which more… Read More