WP_Term Object
(
    [term_id] => 14325
    [name] => Accellera
    [slug] => accellera
    [term_group] => 0
    [term_taxonomy_id] => 14325
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 28
    [filter] => raw
    [cat_ID] => 14325
    [category_count] => 28
    [category_description] => 
    [cat_name] => Accellera
    [category_nicename] => accellera
    [category_parent] => 386
    [is_post] => 
)
            
DVCon 2024 800 x 100 SemiWiki
WP_Term Object
(
    [term_id] => 14325
    [name] => Accellera
    [slug] => accellera
    [term_group] => 0
    [term_taxonomy_id] => 14325
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 28
    [filter] => raw
    [cat_ID] => 14325
    [category_count] => 28
    [category_description] => 
    [cat_name] => Accellera
    [category_nicename] => accellera
    [category_parent] => 386
    [is_post] => 
)

UVM/SystemVerilog: Verification and Debugging

UVM/SystemVerilog: Verification and Debugging
by Daniel Payne on 05-13-2013 at 2:45 pm

At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner… Read More


Accelera Technical Excellence Award

Accelera Technical Excellence Award
by Paul McLellan on 11-30-2012 at 3:46 pm

The Accellera Systems Initiative, most well-known for driving the standardization of various aspects of Verilog and SystemVerilog before handing the standards off to the IEEE, has announced that nominations are open for the 2013 Technical Excellence Award. This recognizes outstanding contributions in the creation of EDA… Read More