“Inverse lithography technology (ILT) represents the most significant EDA advance in the last two decades.” Danping Peng from TSMC made that assertion at the recent SPIE Advanced Lithography + Patterning Conference, in his talk entitled: ILT for HVM: History, Present, and Future. This article summarizes the highlights… Read More
0.55 High-NA Lithography Update
At the recent SPIE Advanced Lithography + Patterning Conference, Mark Phillips from Intel gave an insightful update on the status of the introduction of the 0.55 high numerical aperture extreme ultraviolet lithography technology. Mark went so far as to assert that the development progress toward high-NA EUV would support … Read More
TSMC N3 will be a Record Setting Node!
With the TSMC Technical Symposium coming next month there is quite a bit of excitement inside the fabless semiconductor ecosystem. Not only will TSMC give an update on N3, we should also hear details of the upcoming N2 process.
Hopefully TSMC will again share the number of tape-outs confirmed for their latest process node. Given… Read More
Intel and the EUV Shortage
In my “The EUV Divide and Intel Foundry Services” article available here, I discussed the looming EUV shortage. Two days ago, Intel announced their first EUV tool installed at their new Fab 34 in Ireland is a tool they moved from Oregon. This is another indication of the scarcity of EUV tools.
I have been tracking EUV system production… Read More
Can Intel Catch TSMC in 2025?
At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation.
ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the clear leader. Following that conference,… Read More
Intel Best Practices for Formal Verification
Dynamic event-based simulation of RTL models has traditionally been the workhorse verification methodology. A team of verification engineers interprets the architectural specification to write testbenches for various elements of the design hierarchy. Test environments at lower levels are typically exercised then … Read More
TSMC’s Reliability Ecosystem
TSMC has established a leadership position among silicon foundries, based on three foundational principles:
- breadth of technology support
- innovation in technology development
- collaboration with customers
Frequent SemiWiki readers have seen how these concepts have been applied to the fabrication and packaging technology… Read More
The EUV Divide and Intel Foundry Services
The EUV Divide
I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.
If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production… Read More
How Intel will Beat Samsung
Now that Intel is back in the foundry business, and with the Tower Semiconductor acquisition they are definitely back in the foundry business, Samsung will be the biggest foundry loser here.
You can break the IDM foundry business into two parts: First, and foremost, the NOT TSMC Business. Second is the the Better PPA (Power/Performance,… Read More
Intel Evolution of Transistor Innovation
Intel recently released an exceptional video providing an insightful chronology of MOS transistor technology. Evolution of Transistor Innovation is a five-minute audiovisual adventure, spanning 50 years of Moore’s Law. Some of the highlights are summarized below, with a few screen shot captures – the full video is definitely… Read More


AI RTL Generation versus AI RTL Verification