At Mentor’s U2U this afternoon I attended a presentation on TSMC’s use of Calibre PERC (it is a programmable electrical rule checker) for qualification of IP in TSMC’s IP9000 program. I’ve written about this before here. Basically IP providers at N20SOC, N16FF, and below are required to use PERC to guarantee… Read More
FD-SOI, FinFET, 3D in Monterey
Last night the IEEE Silicon Valley Chapter had a panel session that was in some ways a preview of some of what will be discussed at the Electronic Design Process Symposium in Monterey next Thursday and Friday. At EDPS Herb Reiter organized a session on FinFET, 3DIC and FD-SOI (sort of how many buzzwords can you get into one set of titles).… Read More
Who Wants to Live in Malta?
Who wants to live in Malta? A beautiful island in the eastern Mediterranean with wonderful food…wait, that’s the wrong Malta. I’m talking about the one in upstate New York where GlobalFoundries have their big fab 8 and also their technology development center (also known as fab 8.1).
So why would you want to … Read More
What is Next for GLOBALFOUNDRIES?
In response to changing industry dynamics, AMD announced in October 2008 a new strategy to focus exclusively on the design phase of semiconductor product development. To achieve that strategy, AMD partnered with Advanced Technology Investment Company (ATIC) of Abu Dhabi to create a new joint venture company designed to become… Read More
FinFET Custom Design
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor,… Read More
Imagine what all the DLP technology can do for you
Light has become integral part of most of the electronic devices we use today in any sphere of influence; personal, entertainment, consumer, automotive, medical, security, and industrial and so on. It’s obvious; along with IoT (Internet-of-Things) devices, the devices to illuminate and display things will play a major role… Read More
Handel Jones on FD-SOI vs FinFET
Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis… Read More
Sewn open: Arduino and soft electronics
As several other recent threads on SemiWiki have pointed out, the term “wearables” is a bit amorphous right now. The most recognizable wearable endeavors so far are the smartwatch and fitness band, but these are far from the only categories of interest.
There is another area of wearable wonder beginning to get attention: clothing,… Read More
Triple Patterning
As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.
In the litho world they call double patterning… Read More
Atmel on Tour at AT&T Park
OK, it’s not exactly AT&T park…it’s the parking lot. But they have a huge semi loaded up with lots of cool Atmel stuff to show off some of the things that their customers are doing with their microcontrollers and display technology, primarily focused on the internet of things (IoT). I went down to check it … Read More
MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency