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RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026

RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026
by Admin on 08-24-2026 at 12:00 pm

RISC V at 16 Hot Chips

RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I,… Read More


CEO Interview with Sumeet Kumar of Innatera

CEO Interview with Sumeet Kumar of Innatera
by Daniel Nenni on 08-23-2026 at 8:00 am

SK Headshot 2 (1)

Dr. Sumeet Kumar is CEO of Innatera, the pioneering Dutch neuromorphic processor company. Dr. Kumar was previously with Intel and Indrion Technologies, and has spent his career in microprocessor development. He co-founded Innatera in 2018 as a spin off from the Delft University of Technology.

Tell us about your company?

When… Read More


Hot Chips 2026: Architectures for the Agentic Computing Era

Hot Chips 2026: Architectures for the Agentic Computing Era
by Daniel Nenni on 08-19-2026 at 2:00 pm

Hot Chips 2026 Agentrys Quadric SemiWiki

Hot Chips 2026, formally the thirty-eighth Symposium on High Performance Chips, arrives at Stanford’s Memorial Auditorium from August 23 through 25 with a program that captures a decisive shift in computer architecture. Peak arithmetic throughput remains important, but the conference is increasingly about system balance:… Read More


CEO Interview with Jerry Chen of Upbeat Technology

CEO Interview with Jerry Chen of Upbeat Technology
by Daniel Nenni on 08-13-2026 at 10:00 am

Jerry Chen CEO Founder Upbeat Technology

Jerry Chen, CEO and Founder of Upbeat Technology, received his Master of Science in ECE from the University of Texas at Austin. Started working as an IC design engineer in Silicon Valley at Intel, Lucent, Apple, and Procket Network since 1995. Later transitioned into Technical Marketing roles, serving as Director of Marketing… Read More


Podcast EP359: The Benefits of the SiFive Smart Flow™ Technology with David Kravitz

Podcast EP359: The Benefits of the SiFive Smart Flow™ Technology with David Kravitz
by Daniel Nenni on 08-07-2026 at 10:00 am

Daniel is joined by David Kravitz, Senior Principal Engineer at SiFive, the pioneer of the RISC- V computing revolution. A veteran silicon architect with decades of experience designing high-performance processors ranging from VAX and Alpha to MIPS and ARM, David led the team behind some of the most critical breakthroughs in… Read More


How Fast Can a Performance Model Actually Be Built?

How Fast Can a Performance Model Actually Be Built?
by Admin on 07-26-2026 at 4:00 pm

SimplEx MicroCircuitSutra Performance Model 2026 07 20 Fig

By Thang Tran, CEO of Simplex Micro and Umesh Sisodia, CEO of CircuitSutra

Performance models have a reputation problem. They’re often treated as a long-lead, high-effort undertaking — something a design team commits to early and then waits on for months before it’s useful. The development of SimplEx Micro’s… Read More


RISC-V Advantage in Accelerator Control Highlights System Verification Challenges

RISC-V Advantage in Accelerator Control Highlights System Verification Challenges
by Bernard Murphy on 07-22-2026 at 6:00 am

Breker synthesis engine

When considering best-fit applications for RISC-V, the appeal of extending the instruction set and competitive pricing for storage and edge applications has been pretty clear. But I have always struggled to understand the appeal in head-on competition with Arm in premium applications such as servers and infrastructure systems.… Read More


COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore “EDA+IP” Synergy for the AI Era

COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore “EDA+IP” Synergy for the AI Era
by Daniel Nenni on 06-25-2026 at 6:00 am

AX66

COMPUTEX 2026 officially concluded under the theme “AI Together,” bringing the global semiconductor and computing ecosystem together to showcase the latest advances in artificial intelligence, HPC, and intelligent systems. While AI accelerators and advanced computing platforms dominated the exhibition floor, one collaboration… Read More


AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk

AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk
by Daniel Nenni on 06-22-2026 at 10:00 am

AION Silicon Architecting Smarter SoCs with RISC V

As semiconductor complexity accelerates across AI, automotive, and edge computing markets, SoC architecture has become a critical determinant of commercial success. Modern silicon programs must simultaneously achieve aggressive performance-per-watt targets, support evolving workloads, and maintain manageable development… Read More


RISC-V and AI: The Architecture Shift Is Now

RISC-V and AI: The Architecture Shift Is Now
by Daniel Nenni on 06-17-2026 at 10:00 am

RISC V and AI The Architecture Shift Is Now

The semiconductor industry has experienced several defining transitions over the last three decades. We moved from single-core to multicore processors, from ASIC-centric designs to IP-based SoCs, and from monolithic integration to heterogeneous architectures. Today, another transition is underway, one that may ultimately… Read More