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July 27, 2019August 1, 2019

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops
by Swamy Irrinki on 07-27-2019 at 4:00 am
Categories: Events, IP, RISC-V, SiFive

Last year we hosted several SiFive Tech Symposiums in India to help promulgate the RISC-V ecosystem in the region. The enthusiastic reception from those in industry as well as students and faculty at India’s most esteemed universities was inspiring. This July and August, we’re bringing the SiFive Tech Symposium back to India,… Read More

June 28, 2019June 28, 2019

2019 GSA Silicon Summit and SiFive

2019 GSA Silicon Summit and SiFive
by Daniel Nenni on 06-28-2019 at 8:00 am
Categories: Events, IP, RISC-V, SiFive
2 Comments

Naveed Sherwani, President and CEO of SiFive, did the keynote for this year’s Silicon Summit. This is one of the premier events for the C level executives in Silicon Valley, absolutely. Naveed is one of the top visionaries for the semiconductor industry and he certainly did not disappoint this time or any other time in my experience.… Read More

June 17, 2019June 19, 2019

Considering SiFive: What Should I Get to Implement a RISC-V Core?

Considering SiFive: What Should I Get to Implement a RISC-V Core?
by Randy Smith on 06-17-2019 at 10:00 am
Categories: RISC-V, IP, SiFive

I have an old weathered leather-clad black notebook with a National Semiconductor logo on its face that I have used since 2001. It has sentimental value to me. First, it reminds me of where I was on 9/11, having breakfast with a group of attendees to National Semiconductor’s executive event in Laguna Niguel, CA. We were going to play… Read More

June 14, 2019June 13, 2019

#56thDAC SerDes, Analog and RISC-V sessions

#56thDAC SerDes, Analog and RISC-V sessions
by Eric Esteve on 06-14-2019 at 5:00 am
Categories: Events, IP, IPnest, RISC-V, Semiconductor Services
2 Comments

The good news is that the next five DAC events will take place in Moscone Center in San Francisco! If going to Las Vegas from the Bay area is an easy trip, coming from Europe to Las Vegas makes it a 24+hours journey… One obvious consequence was the poor attendance to the exhibition floor. But let’s be positive and notice that the number… Read More

June 10, 2019June 10, 2019

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

The RISC-V Revolution is Sweeping Across the APAC Region and Australia
by Daniel Nenni on 06-10-2019 at 9:14 pm
Categories: Events, RISC-V, IP, SiFive

Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney

As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence of market-ready… Read More

May 20, 2019May 19, 2019

Learning on the Edge Investment Thesis

Learning on the Edge Investment Thesis
by Jim Hogan on 05-20-2019 at 5:00 am
Categories: EDA, RISC-V, Synopsys, TSMC
2 Comments

It is said that it will cost as much as $600M to develop a 5nm chip. At that price, only a few companies can afford to play, and with that amount of cash in, innovation is severely limited.

At the same time, there is a stampede in the artificial intelligence (AI) market where around 60 startups have appeared, many of which have already … Read More

May 12, 2019

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!
by Daniel Nenni on 05-12-2019 at 4:00 pm
Categories: Events, RISC-V, IP, SiFive

Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam
Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It’s invigorating to see how the worldwide semiconductor ecosystem is energized and… Read More

April 9, 2019

IC Integrity Thesis

IC Integrity Thesis
by Jim Hogan on 04-09-2019 at 12:00 pm
Categories: EDA, Onespin, RISC-V

Most of my investments are associated with large changes in the semiconductor industry. These changes create opportunities for new and disruptive technologies. I also look to find solutions that provide a compelling reason to adopt a new technology or approach. When talking about a new approach, it often takes longer to overcome… Read More

March 26, 2019

Verification 3.0 Holds it First Innovation Summit

Verification 3.0 Holds it First Innovation Summit
by Randy Smith on 03-26-2019 at 5:00 am
Categories: Blue Pearl Software, Breker Systems, Concept Engineering, EDA, Events, Methodics, RISC-V, SiFive

Last week I attended the first Verification 3.0 Innovation Summit held at Levi’s Stadium in Santa Clara along with about 90 other interested engineers and former engineers (meaning marketing and sales people, like me). There was a great vibe and feel to the event as it exuded an energy level that I have not felt at an EDA event in years.… Read More

March 20, 2019

The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II

The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II
by Camille Kokozaki on 03-20-2019 at 5:00 am
Categories: RISC-V, IP, SiFive

During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded… Read More

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eFPGA – "What a great idea! But I have no idea how I’d use it!" Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry The Brave New World of Customized Memory Embedded FPGA: The Fabric for Optimized Machine Learning VLSI Design Methodology Development Enabling Efficient Engineering Infrastructure: Streamline your development resources and increase engineering productivity Desinging Complex SoCs and Dealing with Multiple File Formats? How ASIC/SoC Prototyping Solutions Can Help You! Flexible, Multiprotocol IO’s in 7nm FinFets REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [category_96] => 1 [category_6435] => 1 [category_95] => 1 [category_157] => 1 [category_50] => 1 [category_13] => 1 [category_90] => 1 [category_89] => 1 [category_3611] => 1 [category_178] => 1 [category_14418] => 1 [category_51] => 1 [category_97] => 1 [cpt_page] => 1 [others_blog_page] => 1 [category_44] => 1 [category_5] => 1 [category_32] => 1 [category_22] => 1 ) [display_widget_mobile] => 1 )

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SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

2019 GSA Silicon Summit and SiFive

Considering SiFive: What Should I Get to Implement a RISC-V Core?

#56thDAC SerDes, Analog and RISC-V sessions

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

Learning on the Edge Investment Thesis

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

IC Integrity Thesis

Verification 3.0 Holds it First Innovation Summit

The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II

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