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WP_Term Object
(
    [term_id] => 16126
    [name] => Lithography
    [slug] => lithography
    [term_group] => 0
    [term_taxonomy_id] => 16126
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 164
    [filter] => raw
    [cat_ID] => 16126
    [category_count] => 164
    [category_description] => 
    [cat_name] => Lithography
    [category_nicename] => lithography
    [category_parent] => 0
    [is_post] => 
)

ASML Update SEMICON West 2023

ASML Update SEMICON West 2023
by Scotten Jones on 07-27-2023 at 10:00 am

12494 34 Bart Smeets Supporting future DRAM overlay and EPE roadmaps with the NXT2100i Page 21

At SEMICON West I had a chance to catch up with Mike Lercel of ASML. In this article I am going to combine ASML presentation material from the SPIE Advanced Lithography Conference, Mike’s SEMICON presentation, my discussions with Mike at SEMICON and a few items from ASML’s recent earnings call.

DUV

ASML continues to improve DUV systems.… Read More


NILS Enhancement with Higher Transmission Phase-Shift Masks

NILS Enhancement with Higher Transmission Phase-Shift Masks
by Fred Chen on 07-24-2023 at 8:00 am

Figure 1. NILS is improved

In the assessment of wafer lithography processes, normalized image log-slope (NILS) gives the % change in width for a given % change in dose [1,2]. A nominal NILS value of 2 indicates 10% change in linewidth for 10% change in dose; the % change in linewidth is inversely proportional to the NILS. In a previous article [2], it was shown… Read More


Assessing EUV Wafer Output: 2019-2022

Assessing EUV Wafer Output: 2019-2022
by Fred Chen on 06-26-2023 at 6:00 am

Assessing EUV Wafer Output 2019 2022

At the 2023 SPIE Advanced Lithography and Patterning conference, ASML presented an update on its EUV lithography systems in the field [1]. The EUV wafer exposure output was presented and is shown below in table form:

From this information, we can attempt to extract and assess the EUV wafer output per quarter. First, since there … Read More


Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing

Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing
by Fred Chen on 06-19-2023 at 6:00 am

Brightfield (red) and darkfield (purple) sidelobes in 84 nm

Current 1a-DRAM and 5/4nm foundry nodes have minimum pitches in the 28 nm pitch range. The actual 28 nm pitch patterns are one-dimensional active area fins (for both DRAM and foundry) as well as one-dimensional lower metal lines (in the case of foundry). One can imagine that, for a two-dimensional routing pattern, both horizontal… Read More


A Primer on EUV Lithography

A Primer on EUV Lithography
by Fred Chen on 06-02-2023 at 6:00 am

Litho historical trend Fig 1

Extreme ultraviolet (EUV) lithography systems are the most advanced lithography systems in use today. This article is a basic primer on this important yet complex technology.

The Goal: A Smaller Wavelength

The introduction of 13.5 nm wavelength continues a trend the semiconductor industry had been following a wavelength reduction… Read More


SPIE 2023 – imec Preparing for High-NA EUV

SPIE 2023 – imec Preparing for High-NA EUV
by Scotten Jones on 05-17-2023 at 6:00 am

Figure 1 Pellicle Transmission

The SPIE Advanced Lithography Conference was held in February. I recently had the opportunity to interview Steven Scheer, vice president of advanced patterning process and materials at imec and review selected papers that imec presented.

I asked Steve what the overarching message was at SPIE this year, he said readiness for … Read More


Curvilinear Mask Patterning for Maximizing Lithography Capability

Curvilinear Mask Patterning for Maximizing Lithography Capability
by Fred Chen on 05-09-2023 at 10:00 am

Curvilinear 1

Masks have always been an essential part of the lithography process in the semiconductor industry. With the smallest printed features already being subwavelength for both DUV and EUV cases at the bleeding edge, mask patterns play a more crucial role than ever. Moreover, in the case of EUV lithography, throughput is a concern, … Read More


Reality Checks for High-NA EUV for 1.x nm Nodes

Reality Checks for High-NA EUV for 1.x nm Nodes
by Fred Chen on 04-26-2023 at 6:00 am

Reality Checks for High NA EUV for 1.x nm Nodes

The “1.xnm” node on most roadmaps to indicate a 16-18 nm metal line pitch [1]. The center-to-center spacing may be expected to be as low as 22-26 nm (sqrt(2) times line pitch). The EXE series of EUV (13.5 nm wavelength) lithography systems from ASML feature a 0.55 “High” NA (numerical aperture), targeted… Read More


LAM Not Yet at Bottom Memory Worsening Down 50%

LAM Not Yet at Bottom Memory Worsening Down 50%
by Robert Maire on 04-24-2023 at 10:00 am

LAM RESEARCH Vantex external chamber lrg 300x300

-Lam reported in line results on reduced expectations
-Guidance disappoints as memory decline continues
-Memory capex down 50% but still sees “further declines”
-Lam ties future to EUV maybe not good idea after ASML report

Lam comes in above grossly already reduced expectations
and misses on guidance

We always … Read More


ASML Wavering- Supports our Concern of Second Leg Down for Semis- False Bottom

ASML Wavering- Supports our Concern of Second Leg Down for Semis- False Bottom
by Robert Maire on 04-21-2023 at 8:00 am

Semiconductor False Bottom

-ASML weakness is evidence of deeper chip down cycle
-When ASML sneezes other chip equip makers catch a cold
-Will backlog last long enough? Will EUV demand hold up?
-“Unthinkable” event, litho cancelations, could shock industry

ASML has in line quarter but alarm bells ring on wavering outlook

ASML reported Euro6.7B… Read More