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Is Your Interconnect Strategy Scalable?

Is Your Interconnect Strategy Scalable?
by Bernard Murphy on 05-09-2023 at 6:00 am

Design min

“Strategy” is a word sometimes used loosely to lend an aura of visionary thinking, but in this context, it has a very concrete meaning. Without a strategy, you may be stuck with decisions you made on a first-generation design when implementing follow-on designs. Or face major rework to correct for issues you hadn’t foreseen. Making… Read More


Interconnect Under the Spotlight as Core Counts Accelerate

Interconnect Under the Spotlight as Core Counts Accelerate
by Bernard Murphy on 04-06-2023 at 6:00 am

Core counts min

In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware delivered improved performance/area/power metrics every year, allowing software to expand in complexity and deliver more capability… Read More


Physically Aware NoC Design Arrives With a Big Claim

Physically Aware NoC Design Arrives With a Big Claim
by Bernard Murphy on 02-23-2023 at 6:00 am

NoC manual flow min

I wrote last month about physically aware NoC design, so you shouldn’t be surprised that Arteris is now offering exactly that capability 😊. First, a quick recap on why physical awareness is important, especially below 16nm. Today, between the top level and subsystems a state-of-art SoC may contain anywhere from five to twenty … Read More


Taming Physical Closure Below 16nm

Taming Physical Closure Below 16nm
by Bernard Murphy on 01-30-2023 at 6:00 am

NoC floorplan

Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design.  Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and… Read More


Arteris IP Acquires Semifore!

Arteris IP Acquires Semifore!
by Daniel Nenni on 01-10-2023 at 5:45 am

Arteris Ip Magillem Semifore 3

The semiconductor ecosystem consolidation continues with an interesting acquisition of an EDA company by an IP company. Having worked with both Arteris and Semifore over the past few years I can tell you by personal experience that this is one of those 1+1=3 types of acquisitions, absolutely.

Semifore was founded in 2006 by a team… Read More


Arm and Arteris Partner on Automotive

Arm and Arteris Partner on Automotive
by Bernard Murphy on 09-28-2022 at 6:00 am

Arteris Arm partnership

Whenever a new partnership is announced, the natural question is, “why?” What will this partnership make possible that wasn’t already possible with those two companies working independently? I talked yesterday with Frank Schirrmeister of Arteris on the partnership. (Yes, Frank is now at Arteris). And I just got off an Arm press… Read More


Coherency in Heterogeneous Designs

Coherency in Heterogeneous Designs
by Bernard Murphy on 09-01-2022 at 6:00 am

Ncore application

Ever wonder why coherent networks are needed beyond server design? The value of cache coherence in a multi-core or many-core server is now well understood. Software developers want to write multi-threaded programs for such systems and expect well-defined behavior when accessing common memory locations. They reasonably expect… Read More


Scalability – A Looming Problem in Safety Analysis

Scalability – A Looming Problem in Safety Analysis
by Stefano Lorenzini on 07-28-2022 at 6:00 am

Figure 2 FMEDA white paper

Scalability – A Looming Problem in Safety Analysis

The boundless possibilities of automation in cars and other vehicles have captivated designers to the point that electronic content is now a stronger driver of differentiation than any other factor. It accounts for a substantial fraction of material cost in any of these vehicles.… Read More


Scaling Safety Analysis. Reusability for FMEDA

Scaling Safety Analysis. Reusability for FMEDA
by Bernard Murphy on 06-23-2022 at 6:00 am

FMEDA generation

It is common when a new type of analysis is introduced in almost any domain that it works well enough for a while. Until it begins to struggle with growing problem size, prompting refinements to the methodology to allow continued scaling. We see this routinely in analytics for SoC design, so it should not be a big surprise that safety… Read More


Why Traceability Now? Blame Custom SoC Demand

Why Traceability Now? Blame Custom SoC Demand
by Bernard Murphy on 05-18-2022 at 6:00 am

Traceability abstract min

In the SoC world, we can’t believe our good luck. Every product maker now wants bespoke silicon solutions with the most advanced AI, communications, SLAM, etc. Which is fantastic for business, but this level of demand also drags us into a new level of accountability, especially in requirements traceability. Time was that only … Read More