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FPGA
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"The Year of the eFPGA" 2017 Recap

"The Year of the eFPGA" 2017 Recap
by Tom Dillinger on 12-22-2017 at 7:00 am
Categories: eFPGA, Flex Logix, FPGA, IP

This past January, I had postulated that 2017 would be the “Year of the Embedded FPGA”, as a compelling IP offering for many SoC designs (link). As the year draws to a close, I thought it would be interesting to see how that prediction turned out.

The criteria that would be appropriate metrics include: increasing capital investment;… Read More

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Aldec and High-Performance Computing

Aldec and High-Performance Computing
by Bernard Murphy on 12-21-2017 at 7:00 am
Categories: Aldec, EDA, Events, FPGA

Aldec continues to claim a bigger seat at the table, most recently in their attendance at SC17, the supercomputing conference hosted last month in Denver. I’m really not sure how to categorize Aldec now. EDA company seems to miss the mark by a wide margin. Prototyping company? Perhaps, though they have a much stronger focus on end-applications… Read More

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When Invaluable Kills Business

When Invaluable Kills Business
by Frederic Leens on 12-11-2017 at 7:00 am
Categories: EDA, FPGA
6 Comments

Productivity is notoriously hard to sell. I recently visited a company where the engineering team wanted to evaluate one of our FPGA debug and analysis products on an existing board. This board had an FPGA that we supported and had all the required connectivity – it could just be used ‘out of the box’. Our tool – Exostiv… Read More

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What are you ready to mobilize for FPGA debug?

What are you ready to mobilize for FPGA debug?
by Frederic Leens on 12-04-2017 at 7:00 am
Categories: EDA, FPGA

There are 3 common misconceptions about debugging FPGA with the real hardware:

[LIST=1]

  • Debugging happens because the engineers are incompetent.
  • FPGA debugging on hardware ‘wastes’ resources.
  • A single methodology should solve ALL the problems.
    • … Read More
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    Scale the tools not your expectations

    Scale the tools not your expectations
    by Frederic Leens on 11-16-2017 at 12:00 pm
    Categories: EDA, FPGA

    The complexity of silicon chips is exploding. Actually, it has been growing at a tremendous speed for decades. So far, the semiconductor industry has been successful at providing new ways to master new levels of complexity, over and over again.

    Standardizing hardware platforms, using higher-level languages with a knowledge… Read More

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    DesignShare is all About Enabling Design Wins!

    DesignShare is all About Enabling Design Wins!
    by Daniel Nenni on 11-08-2017 at 7:00 am
    Categories: eFPGA, Flex Logix, FPGA, IP, RISC-V, SiFive
    5 Comments

    One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges.… Read More

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    The perfect pairing of SOCs and embedded FPGA IP

    The perfect pairing of SOCs and embedded FPGA IP
    by Tom Simon on 10-30-2017 at 12:00 pm
    Categories: Achronix, eFPGA, Events, FPGA, IP

    In life, there are some things that just go together. Imagine the world without peanut butter and jelly, eggs and potatoes, telephones and voicemail, or the internet and search engines. In the world of computing there are many such examples – UARTS and FIFO’s, processor cores and GPU’s, etc. Another trait all these things have is… Read More

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    Timing Analysis for Embedded FPGA’s

    Timing Analysis for Embedded FPGA’s
    by Tom Dillinger on 10-25-2017 at 7:00 am
    Categories: eFPGA, Flex Logix, FPGA, IP
    1 Comment

    The initial project planning for an SoC design project faces a difficult engineering decision with regards to the “margin” that should be included as part of timing closure. For cell-based blocks, the delay calculation algorithms within the static timing analysis (STA) flow utilize various assumptions to replace… Read More

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    Webinar: Optimizing QoR for FPGA Design

    Webinar: Optimizing QoR for FPGA Design
    by Bernard Murphy on 10-22-2017 at 12:00 pm
    Categories: EDA, Events, FPGA, Synopsys

    You might wonder why, in FPGA design, you would go beyond simply using the design tools provided by the FPGA vendor (e.g. Xilinx, Intel/Altera and Microsemi). After all, they know their hardware platform better than anyone else, and they’re pretty good at design software too. But there’s one thing none of these providers want to… Read More

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    How standard-cell based eFPGA IP can offer maximum safety, flexibility and TTM?

    How standard-cell based eFPGA IP can offer maximum safety, flexibility and TTM?
    by Eric Esteve on 10-19-2017 at 12:00 pm
    Categories: eFPGA, FPGA, IP, Menta

    Writing a white paper is never tedious, and when the product or the technology is emerging, it can become fascinating. Like for this white paper I have written for Menta “How Standard Cell Based eFPGA IP are Offering Maximum Flexibility to New System-on-Chip Generation”. eFPGA technology is not really emerging, but it’s fascinating… Read More