Semiwiki 400x100 1 final
WP_Term Object
(
    [term_id] => 106
    [name] => FPGA
    [slug] => fpga
    [term_group] => 0
    [term_taxonomy_id] => 106
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 339
    [filter] => raw
    [cat_ID] => 106
    [category_count] => 339
    [category_description] => 
    [cat_name] => FPGA
    [category_nicename] => fpga
    [category_parent] => 0
    [is_post] => 
)
FPGA
Posted on

Beyond one FPGA comfort zone

Beyond one FPGA comfort zone
by Don Dingee on 04-29-2013 at 5:00 pm
Categories: Aldec, EDA, FPGA

Unless you are a small company with one design team, the chance you have standardized on one FPGA vendor for all your needs, forever and ever, is unlikely. No doubt you probably have a favorite, because of the specific class of part you use most often or the tool you are most familiar with, but I’d bet you use more than one FPGA vendor routinely.… Read More

Posted on

FPGAs – The Possibilities are Endless – Almost

FPGAs – The Possibilities are Endless – Almost
by Luke Miller on 04-26-2013 at 8:00 pm
Categories: FPGA, Xilinx

Has your wife ever said “Your name, I’m not a computer”? Well maybe mine has. I know what you are thinking… This guy is married? Yup, I over achieved too. Have child #7 on the way Lord willing, so you probably guessed I don’t follow much of the world’s planning and such. Like you, no one in my house really understands what I do, nor cares … Read More

Posted on

Morris Chang on Altera and Intel

Morris Chang on Altera and Intel
by Daniel Nenni on 04-25-2013 at 7:00 pm
Categories: Foundries, FPGA, Intel, TSMC


If you want to know why I have written so much about TSMC in the past five years here it is: TSMC executives are approachable, personable, answer questions straight on, and have yet to lead me astray. If you want an example of this read the Chairman’s comments on the TSMC Q1 2013 earnings call transcript.

“On 16-nanometer FinFET, we … Read More

Posted on

FPGA + MATLAB = FATLAB

FPGA + MATLAB = FATLAB
by Luke Miller on 04-21-2013 at 7:00 pm
Categories: FPGA, Xilinx

Now Michael Bloomberg probably wouldn’t want FATLAB but let’s face it, to think like him you need a lot of education, alot. He may be banning 14nm because it will increase FPGAs densities and thus the consumer as well. Stay tuned. After some comments from my dear readers, one who said to watch it with respect to my harshness about… Read More

Posted on

FPGAS – The New Single Board Computers?

FPGAS – The New Single Board Computers?
by Luke Miller on 04-16-2013 at 10:00 pm
Categories: FPGA, Xilinx

I have always felt that FPGAs have been the red haired step child of Silicon Valley. Software weenies have hated them, they are mysterious and take too long to route. Even though they can be massively parallel and the most deterministic piece of silicon you can buy besides a million dollar ASIC, the GPU steals their glory, for now. … Read More

Posted on

Xilinx: Hide the RTL

Xilinx: Hide the RTL
by Paul McLellan on 04-16-2013 at 7:30 pm
Categories: FPGA, Xilinx

Tom Feist of Xilinx presented here at the GlobalPress Electronics Summit about their strategy to take design abstraction up another level. In the SoC world, we are still pretty much stuck at the RTL level and have moved to higher abstractions by using an IP strategy. But at least all IC designers are RTL-literate.


Xilinx, in the Vivado… Read More

Posted on

Altera, Intel, TSMC, ARM: the Plot Thickens

Altera, Intel, TSMC, ARM: the Plot Thickens
by Paul McLellan on 04-16-2013 at 7:15 pm
Categories: Arm, FPGA, Intel, TSMC

Vince Hu of Altera presented us her at the GlobalPress Electronics Summit on their process roadmap. Since just a month or two ago they announced that Intel would be their foundry at 14nm, everyone wanted to get a better idea of what was really going on.

At 28nm, Altera use 2 processes, TSMC 28HP (for high end Stratix-5 devices) and TSMC… Read More

Posted on

Ivo Bolsens’ Keynote on the All-Programmable SoC

Ivo Bolsens’ Keynote on the All-Programmable SoC
by Paul McLellan on 04-13-2013 at 8:00 pm
Categories: FPGA, Xilinx

Ivo Bolsens, the CTO of Xilinx, is giving the opening keynote at the Electronic Design Process Symposium (EDPS) in Monterey on Thursday and Friday this coming week. The title of his keynote is The All Programmable SoC – At the Heart of Next Generation Embedded Systems. He covers a lot of ground but the core of his presentation… Read More

Posted on

How to make ESL really work – see EDPS

How to make ESL really work – see EDPS
by John Swan on 04-12-2013 at 6:53 pm
Categories: FPGA, Xilinx

The Electronic Design Process Symposium (EDPS) is April 18 & 19 in Monterey. The workshop style Symposium is in its 20[SUP]th[/SUP] year. The first session is titled “ESL & Platforms”, which immediately follows the opening Keynote address by Ivo Bolsens, CTO of Xilinx.

In his keynote presentation Ivo will present how… Read More

Posted on

High Level Synthesis – It’s for Real

High Level Synthesis – It’s for Real
by Luke Miller on 04-11-2013 at 8:30 pm
Categories: FPGA, Xilinx

It was spring 2010 and I was asked to attend an HLS (High Level Synthesis) meeting. To be honest I cringed, after my bad relationship with Accel DSP and broken promises my heart was all walled up and needed counseling. But my management had a way of making me an offer I could not refuse, like keeping my job. So reluctantly I went. Does your… Read More