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SiP is the new SoC @ 56thDAC

SiP is the new SoC @ 56thDAC
by Tom Dillinger on 06-19-2019 at 6:48 pm

The emergence of 3D packaging technology has been accompanied by the term “more than Moore”, to reflect the increase in areal circuit density at a rate that exceeds the traditional IC scaling pace associated with Moore’s Law.  At the recent Design Automation Conference in Las Vegas, numerous exhibits on the vendor floor presented… Read More


Meet the Experts @ ES Design West!

Meet the Experts @ ES Design West!
by Daniel Nenni on 06-18-2019 at 10:00 am

SEMICON West and ES Design West are right around the corner here in San Francisco and I wanted to point out the Meet the Experts segment in the appropriately named Meet the Experts Theater. Great idea really and a super great line-up. The best part of course is actually meeting the experts. Over my 35 year semiconductor career I have… Read More


Synopsys Low Power Workshop Offers Breadth and Depth

Synopsys Low Power Workshop Offers Breadth and Depth
by Bernard Murphy on 06-18-2019 at 5:00 am

Synopsys seems to particularly excel at these events, whether in half-day tutorials at conferences or, as in this case, in a full-day on-site workshop. You might think there’s not much that can be added in this domain, other than to bring low-power newbies up to speed, but you’d be wrong. This event set the stage with surveys on needs… Read More


#56thDAC SerDes, Analog and RISC-V sessions

#56thDAC SerDes, Analog and RISC-V sessions
by Eric Esteve on 06-14-2019 at 5:00 am

The good news is that the next five DAC events will take place in Moscone Center in San Francisco! If going to Las Vegas from the Bay area is an easy trip, coming from Europe to Las Vegas makes it a 24+hours journey… One obvious consequence was the poor attendance to the exhibition floor. But let’s be positive and notice that the number… Read More


TSMC in the Cloud Update #56thDAC 2019

TSMC in the Cloud Update #56thDAC 2019
by Daniel Nenni on 06-13-2019 at 10:00 am

During my Taiwan visit, prior to Las Vegas, I was fortunate to spend time with Willy Chen and Vivian Jiang to prepare for the cloud panel I moderated at #56thDAC. Willy and Vivian are part of the ever-important Design Infrastructure Marketing Division of TSMC, which includes the internal and external cloud efforts. TSMC first announced… Read More


#56DAC – What’s New with Custom Design Platform

#56DAC – What’s New with Custom Design Platform
by Daniel Payne on 06-12-2019 at 10:00 am

Dave Reed, Synopsys

TSMC attends DAC every year and they do something very savvy, it’s a theatre where they invite all of their EDA and IP partners to present something of interest, followed by a drawing for a prize. At the end of the day they even have a nice prize, like a MacBook Air, which I didn’t win. On Wednesday I watched Dave Reed of SynopsysRead More


The Complexity of Block-Level Placement @ 56thDAC

The Complexity of Block-Level Placement @ 56thDAC
by Tom Dillinger on 06-11-2019 at 10:00 am

The recent Design Automation Conference in Las Vegas was an indication of how the electronics industry is evolving.  In its formative years, DAC was focused on the fundamental algorithms emerging from academic research and industrial R&D, that enabled the continuation of the Moore’s Law complexity curve.  (Indeed, the… Read More


The RISC-V Revolution is Sweeping Across the APAC Region and Australia

The RISC-V Revolution is Sweeping Across the APAC Region and Australia
by Daniel Nenni on 06-10-2019 at 9:14 pm

Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney

As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence of  market-ready… Read More


Samsung Foundry Update 2019

Samsung Foundry Update 2019
by Tom Dillinger on 06-08-2019 at 5:00 am

Samsung Foundry recently held their 4th annual technology forum in Santa Clara.  This article reviews the highlights of the presentations.  There were two prevalent themes throughout – focused execution on the current process roadmap, and the introduction of the 3nm process node features and schedule.

Before getting into … Read More