SEMI, the global industry association advancing the interests of the worldwide electronics supply chain, today (October 19) published a new report, “Global 200mm Fab Outlook to 2018.” According to the report, worldwide 200mm semiconductor wafer fab capacity is forecast at 5.2 million wafer starts per month (wspm) in 2015 and… Read More
Wafer-Level Chip-Scale Packaging Technology Challenges and Solutions
At the recent TSMC OIP symposium, Bill Acito from Cadence and Chin-her Chien from TSMC provided an insightful presentation on their recent collaboration, to support TSMC’s Integrated FanOut (InFO) packaging solution. The chip and package implementation environments remain quite separate. The issues uncovered in bridging… Read More
IMEC and Cadence Disclose 5nm Test Chip
Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.
First off Vassilios really… Read More
Cadence Outlines Automotive Solutions at TSMC OIP Event
I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s… Read More
EDA By the Numbers, Phil Kaufman, Emerging Companies and More
The quarterly numbers are out from the EDAC Market Statistics Service (MSS) for Q2. The headline number is that revenue for the industry increased by 8.5% for Q2 to $1906.5M versus $1759.9M in Q2 last year. The four quarter moving average, that smooths out a lot of seasonality by comparing the most recent four quarters to the prior… Read More
Xilinx Skips 10nm
At TSMC’s OIP Symposium recently, Xilinx announced that they would not be building products at the 10nm node. I say “announced” since I was hearing it for the first time, but maybe I just missed it before. Xilinx would go straight from the 16FF+ arrays that they have announced but not started shipping, and to the… Read More
SEMICON West Preview
Founded in 1971 (2015: 45th year), SEMICON West 2015 is coming to the Moscone Center in San Francisco on from Tuesday, July 14[SUP]th[/SUP] to Thursday, July 16[SUP]th[/SUP]. SEMICON is the premier show for equipment and materials companies supporting the semiconductor, MEMS and solar industries.
The main ways to get value … Read More
Unlock the Key to Ultra-Low Power Design
We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low… Read More
Eyes Meet Innovations at DAC
It gives me a very nice, somewhat nostalgic, feeling after attending the 52[SUP]nd[/SUP] DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D… Read More
Application Specific Integrated Comedy
Tuesday night I got to meet an old colleague. OK, this is DAC, that is hardly a story. I was at the Synopsys media dinner and John Koeter handed out free wristbands to the Stars of IP party taking place later that evening. Remember, Synopsys is #3 in IP overall and #1 in interface IP. Talking of which, earlier in the day I was at the Synopsys… Read More
Quantum Computing Technologies and Challenges