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WP_Term Object
(
[term_id] => 159
[name] => Siemens EDA
[slug] => siemens-eda
[term_group] => 0
[term_taxonomy_id] => 159
[taxonomy] => category
[description] =>
[parent] => 157
[count] => 816
[filter] => raw
[cat_ID] => 159
[category_count] => 816
[category_description] =>
[cat_name] => Siemens EDA
[category_nicename] => siemens-eda
[category_parent] => 157
[is_post] =>
)
WP_Term Object
(
[term_id] => 159
[name] => Siemens EDA
[slug] => siemens-eda
[term_group] => 0
[term_taxonomy_id] => 159
[taxonomy] => category
[description] =>
[parent] => 157
[count] => 816
[filter] => raw
[cat_ID] => 159
[category_count] => 816
[category_description] =>
[cat_name] => Siemens EDA
[category_nicename] => siemens-eda
[category_parent] => 157
[is_post] =>
)
In a two-part series, Lauro Rizzatti examines why three kinds of hardware-assisted verification engines are a must have for today’s semiconductor designs. To do so, he interviewed Siemens EDA’s Vijay Chobisa and Juergen Jaeger to learn more about the Veloce hardware-assisted verification systems.
What follows is part one,… Read More
Rich Edelman of Siemens EDA recently released a paper on this topic. I’ve known Rich since our days together back in National Semi. And I’ve always been impressed by his ability to make a complex topic more understandable to us lesser mortals. He tackles a tough one in this paper – a complex concept (polymorphism) in a complex domain… Read More
3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic of discussion. The technology was originally leveraged for stacking functional blocks with high-bandwidth buses between them. Memory manufacturers and other IDMs were the ones to typically leverage this … Read More
Digital Twins Simplify System Analysisby Dave Bursky on 08-15-2022 at 6:00 amCategories: EDA, Siemens EDA
The ability to digitally replicate physical systems has been used to model hardware operations for many years, and more recently, digital twining technology has been applied to electronic systems to better simulate and troubleshoot the systems. As explained by Bryan Ramirez, Director of Industries, Solutions & Ecosystems,… Read More
Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task… Read More
Tuesday at DAC I had the pleasure of attending the Design on Cloud Theatre where experts from Siemens EDA gave an update on what they’ve been offering to IC and systems designers. I remember attending a cloud presentation from Craig Johnson in 2021, so I was keen to note what had changed in the past 12 months.
Industry Trends,
…
Read More
In 2022 using the cloud for EDA tasks is a popular topic, and at DAC this year I could see a bigger presence from the cloud hardware vendors in the exhibit area, along with a growing stampede of EDA companies. Tuesday at DAC there was a luncheon with experts from Siemens EDA, Google and AMD talking about surge compute. I already knew Michael… Read More
It’s the second day of DAC, and the announcements are coming in at a fast pace, so stay tuned to SemiWiki for all of the latest details. As a long-time SPICE user and industry follower, I’ve witnessed the progression as EDA vendors have connected their SPICE simulators to digital simulators, opening up a bigger world… Read More
When I worked at EDA vendors and attended DAC, one of the most popular questions asked in the booth and suites was simply, “What’s new this year?” It’s a fair question, and yet many semiconductor professionals are so focused on their present project, using their familiar methodology, that they simply… Read More
Amid the alphabet soup of inter-die/chip coherent access protocols, CXL is gaining a lot of traction. Originally proposed by Intel for cross-board and cross-backplane connectivity to accelerators of various types (GPU, AI, warm storage, etc.), a who’s who of systems and chip companies now sits on the board, joined by an equally… Read More