We have talked about metamorphic testing before. Here is a clever application to testing an AMS subsystem. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.… Read More
Electronic Design Automation
Webinar: RF board design flow examples for co-simulating active circuits
In part one of this webinar series, Keysight and Modelithics looked at the use of 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation of high-frequency RF board designs. Part two continues the exploration of RF board design flows for simulating active circuits on boards, again… Read More
Going Beyond DRC Clean with Calibre DE
For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal… Read More
Cut Defects, Not Yield: Outlier Detection with ML Precision
How much perfectly good silicon is being discarded in the quest for reliability? During high-volume chip manufacturing, aggressive testing with strict thresholds may ensure quality but reduces yield, discarding marginal chips that could function flawlessly. On the other hand, prioritizing yield risks allowing defective… Read More
Compute and Communications Perspectives on Automotive Trends
Automotive electronics is a fast-moving space, especially around sensing and distilling intelligence from that sensing. This serves three main pillars: autonomy, electrification and advances in the car cockpit. Autonomy at multiple levels remains an important goal and continues to advance, technically and geographically.… Read More
Video EP2: A Detailed Look at the Most Effective Way to Conquer Clock Jitter with Samia Rashid
In this episode of the Semiconductor Insiders video series, Dan is joined by Samia Rashid, co-founder and president of Infinisim. Samia provides detailed background on clock jitter – what it is, what causes it and the various methods to address the problem. Samia describes the unique clock analysis technology developed… Read More
Siemens Fleshes out More of their AI in Verification Story
While Cadence and Synopsys were sharing a lot of detail over the past few years about what they were doing in AI, Siemens EDA seemed content to offer a very general picture about their intentions without getting into a lot of detail. At DVCon 2025 they finally pulled back the curtain. Why wait until now to announce?
Darron May (Director… Read More
Speeding Up Physical Design Verification for AMS Designs
Custom and analog/mixed-signal IC designs have some unique IP and symmetry checking requirements for physical design. Waiting until the end of the IC layout process to verify IP instances for correctness or proper symmetry will cause project delays, so an approach to perform earlier physical verification makes more sense. … Read More
S2C: Empowering Smarter Futures with Arm-Based Solutions
The tech world is sprinting toward a future where your fridge orders groceries, your car avoids traffic before you hit it, and security cameras don’t just watch—they understand. But behind these innovations lies a messy truth: building the brains for these smart systems is complicated.
Fresh off the 2024 Arm Tech Symposia… Read More
DVCon 2025: AI and the Future of Verification Take Center Stage
The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot