SILVACO 051525 Webinar 800x100 v2
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EDA

Electronic Design Automation

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3D IC @ #48DAC

3D IC @ #48DAC
by Daniel Nenni on 05-23-2011 at 4:54 pm
Categories: EDA, Events

A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this emerging technology in many different forms, as a result the full definition is still somewhat… Read More

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48th Annual Design Automation Conference

48th Annual Design Automation Conference
by Daniel Nenni on 05-23-2011 at 8:08 am
Categories: EDA, Events

The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.

The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow … Read More

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Analyzing and Planning Electro-static Discharge (ESD) Protection

Analyzing and Planning Electro-static Discharge (ESD) Protection
by Paul McLellan on 05-23-2011 at 5:00 am
Categories: Ansys, Inc., EDA

ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.

Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies.… Read More

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Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review

Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review
by Daniel Payne on 05-19-2011 at 5:33 pm
Categories: Cadence, Cliosoft, EDA

Introduction
Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.

What’s New from Cadence in Virtuoso 6.1.5

  • Back2Basics (28nm rule integration, Skill improved with object-oriented, OASIS support, HTML Publisher, Waveform re-written for better Analog support, smaller Waveform
… Read More
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A New Hierarchical 3D Field Solver

A New Hierarchical 3D Field Solver
by Daniel Payne on 05-19-2011 at 2:04 pm
Categories: EDA

Introduction
3D field solvers produce the most accurate netlists of RC values of your IC layout that can then be used in SPICE circuit simulators however most of these solvers produce a flat netlist which tends to simulate rather slowly. Thankfully several years ago the first hierarchical SPICE tools were offered by Nassda (HSIM… Read More

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Electro-static Discharge (ESD)

Electro-static Discharge (ESD)
by Paul McLellan on 05-18-2011 at 4:26 pm
Categories: Ansys, Inc., EDA

Electro-static discharge (ESD) has been a problem since the beginning of IC production. Chips function on power supplies of up to a few volts (depending on the era) whereas ESD voltages are measured in the thousands of volts. When you reach out for your car door handle and a spark jumps across, that is ESD. If you were touching a chip… Read More

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Shakeup at Mentor Graphics

Shakeup at Mentor Graphics
by Daniel Payne on 05-12-2011 at 12:22 pm
Categories: EDA, Siemens EDA

Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:

  • José Maria Alapont, chief executive of the auto parts maker Federal-Mogul
  • Gary Meyers, a director of the chip maker Exar
  • David Schechter, an executive at Mr. Icahn’s investment firm
… Read More
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SOC Realization: How Chips Are Really Designed

SOC Realization: How Chips Are Really Designed
by Paul McLellan on 05-09-2011 at 10:00 pm
Categories: EDA

If you just casually peruse most marketing presentations by EDA companies, you’d come to the conclusion most SoCs are designed from scratch, wrestlilng the monster to the ground with bare hands. But the reality is that most SoCs consist of perhaps 90% IP blocks (many of them memories). That still leaves the remaining 10% … Read More

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Cadence EDA360 is Paper!

Cadence EDA360 is Paper!
by Daniel Nenni on 05-08-2011 at 4:02 pm
Categories: Cadence, EDA

Hard to believe a year has gone by since the big announcement of the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat! Having spent more time on it that I should have, here is my opinion on EDA360 on its first anniversary.

Richard Georing did a very nice anniversary piece “Ten Key… Read More

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Chip Power Models

Chip Power Models
by Paul McLellan on 05-04-2011 at 4:21 pm
Categories: Ansys, Inc., EDA

As the complexity of the chip-package-system (CPS) interactions has increased, the tradeoffs in doing a power and noise analysis has had to gradually increase. As is so often the case in semiconductor designs, issues first arise as second-order effects that can largely be ignored but each process node makes the problem worse … Read More