Banner Electrical Verification The invisible bottleneck in IC design updated 1
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4329
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4329
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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NVM Express: pervasion of PCI Express in SSD based storage

NVM Express: pervasion of PCI Express in SSD based storage
by Eric Esteve on 03-22-2012 at 12:48 pm
Categories: IP, Synopsys

The verification IP (VIP) for Non-Volatile Memory Express (NVMe) announcement from Synopsys is the first fruit issued from the acquisition of ExpertIO. With the proliferation of Nand Flash based storage equipment, or Solid State Drives (SSD), the move from pure SATA based solution was to be expected, sooner or later. Not because… Read More

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What’s Up with SNUG This Year in Santa Clara?

What’s Up with SNUG This Year in Santa Clara?
by Daniel Payne on 03-22-2012 at 11:04 am
Categories: EDA, Synopsys

Next week is a big deal because it’s when Synopsys has their annual user group meeting, SNUG in Santa Clara at the Convention Center from Monday through Wednesday. I’d love to hear if they have made any decisions on the new product roadmap after the Magma acquisition, although it’s probably too early to tell.… Read More

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3D-IC Testing – A 3D perspective to SoC

3D-IC Testing – A 3D perspective to SoC
by Pawan Fangaria on 03-21-2012 at 9:30 am
Categories: EDA, Siemens EDA

In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory… Read More

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According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012

According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
by Eric Esteve on 03-21-2012 at 9:10 am
Categories: Cadence, IP

The launch from Cadence of the PCI Express 3.0 Controller IP was officially done about one year ago, and demonstrated at the June 2011 PCI-SIG Developer’s Conference, where Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller… Read More

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A Chat with John Stabenow

A Chat with John Stabenow
by Daniel Payne on 03-20-2012 at 10:57 am
Categories: Cadence, EDA

John Stabenow is the marketing group director at Cadence for the Virtuoso products and it has been awhile since we last talked, so we met for lunch on Friday at McMenamins in a city called West Linn, half-way between where we both live in Oregon. I had blogged about Interoperability at DAC 2010 and we had a public exchange at Chip Design… Read More

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EDPS Monterey

EDPS Monterey
by Paul McLellan on 03-17-2012 at 8:00 am
Categories: EDA, Events

Every year in Monterey is a relatively small conference that looks at the design process, EDPS, the electronic design process symposium. I gave a keynote there a couple of years ago, but you don’t have to listen to me this time. The keynotes are from:

  • 1st day: Misha Buric, CTO of Altera, talking about SoC FPGAs and other things
… Read More
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Double Patterning and Then The End of Lithography

Double Patterning and Then The End of Lithography
by Paul McLellan on 03-15-2012 at 8:00 am
Categories: EDA, Siemens EDA

I went to a couple more sessions at the Common Platform Technology Forum today, on 20nm double patterning and whatever will we do at 14nm. Basically, this is the end of planar transistors and the end of optical lithography. One session was by IBM scientists about process and one by Michael White of Mentor about double patterning. … Read More

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No Semiconductor Design Cloud Strategy? Really?

No Semiconductor Design Cloud Strategy? Really?
by Andrea Casotto on 03-14-2012 at 6:00 pm
Categories: EDA


I ask my customers about their cloud strategy and they all tell me “none”. The main reason is a red herring: “The legal department will never allow our IP outside our walls”.

Security issues on the cloud are largely solved, as proven by the fact that banks have no problem using external clouds. Behind the curtain, the real reason for… Read More

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Timing Closure for ECOs in your SOC Design

Timing Closure for ECOs in your SOC Design
by Daniel Payne on 03-14-2012 at 1:07 pm
Categories: EDA, Synopsys

I decided to attend a webinar today hosted by Synopsys, “Streamline Your PrimeTime ECO Flow For Fastest Setup, Hold and Timing DRC Closure.” The format was to present slides first then hold for questions until the end. Enough time was spent on questions which made this webinar different than most other webinars I’ve… Read More

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CDNLive: the Keynotes

CDNLive: the Keynotes
by Paul McLellan on 03-13-2012 at 2:24 pm
Categories: Cadence, EDA

There were three keynotes at CDNLive this morning, and one theme ran through them: collaboration. In fact there was one specific instance of collaboration that all three people mentioned. Taping out an ARM Cortex-A15 in TSMC 20nm technology using a Cadence tool flow.

Lip-Bu, Cadence’s CEO, went first. He had some numbers… Read More