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Electronic Design Automation
Collaboration between EDA, Foundry and Design was the key idea today in a webinar hosted by IBM and Cadence about 20nm custom IC design. The three presenters were:
John Stabenow, Cadence
Jeremiah Cessna, Cadence
Keith Barkley, IBM… Read More
There’s this EDA company. They have over 100 tapeouts. They have a $28M in funding. They have 250 people. And you’ve never heard of them. Or at least I hadn’t.
They are ICScape. They started in 2005 with an investment from Acorn Campus Ventures and delivered their first product, ClockExplorer, in 2007 and their… Read More
There is a famous quote (probably attributed to Mark Twain who gets them all by default) “When looking for faults use a mirror not a spyglass.” Of course if you have RTL of your IP or your design then using a SpyGlass is clearly the better way to go. But it is getting even better since there is a new enhanced release, SpyGlass… Read More
One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:
While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More
ARM used to build their own models. By hand. They had an instruction-set simulator (ISS) called ARMulator that was largely intended for software development, and cycle-accurate models that were intended to run within digital simulators for development of the hardware of ARM-based systems.
There were two problems with this … Read More
For many, maybe most, big designs, Apache’s RedHawk is the signoff tool for analyzing issues around power: electromigration, power supply droop, noise, transients and so on. But the latest designs have some issues: they are enormous (so you can’t just analyze them naively any more than you can run a Spice simulation… Read More
At the GSA 3D IC working group meeting, Cadence presented their perspective on 3D ICs. Their view will turn out to be important since the new chair of the 3D IC working group is going to be Ken Potts of Cadence. Once GSA decided the position could not be funded then an independent consultant like Herb Reiter had to bow out and the position… Read More
IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here’ s a list of reliability issues to keep you awake at night:… Read More
If you are in Europe then the CDNLive! EMEA user conference is in Munich at the Dolce Hotel from May 14th to 16th. Like last month’s CDNLive! in Cadence’s hometown San Jose, the conference focuses on sharing fresh ideas and best practices for all aspects of semiconductor design from embedded software down to bare silicon.… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot