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DesignSync update from Dassault Systems at DAC

DesignSync update from Dassault Systems at DAC
by Daniel Payne on 06-24-2012 at 8:10 pm

At DAC on Wednesday Rick Stanton of Dassault Systems gave me an update on what’s new with DesignSync, a design data management tool offered since 1998. Rick and I both worked at Viewlogic in the 90’s along with Dennis Harmon who then founded Synchronicity, later acquired by Dassault Systems.… Read More


Finding RTL Bugs Live Using Formal Techniques

Finding RTL Bugs Live Using Formal Techniques
by Daniel Payne on 06-24-2012 at 8:10 pm

Most of what you see at DAC is canned PowerPoint presentations, however on Tuesday afternoon I spotted a company called Oski Technology that was doing something almost unheard of – they had an engineer debugging a digital design from Nvidia using formal tools live. I later found out the engineer found 4 bugs in just three days… Read More


Webinar: how to reduce mobile device cost and board space with LLI

Webinar: how to reduce mobile device cost and board space with LLI
by Eric Esteve on 06-24-2012 at 2:46 am

LLI Specification has been officially released by the MIPI Alliance, at the occasion of the Mobile World Congress in Barcelona, this year. As indicated by the name, the round-trip latency of the LLI inter-chip connection is fast enough for a mobile phone modem to share an application processor’s memory while maintaining… Read More


Designing a Wafer-Scale Image Sensor for use in X-Rays

Designing a Wafer-Scale Image Sensor for use in X-Rays
by Daniel Payne on 06-22-2012 at 1:32 pm

At Intel we mused about designing wafer-scale integration (WSI) back in the 70’s however I just learned about how Dr.Renato Turchetta at the Science and Technology Facilities Council (STFC) designed a wafer-scale imaging sensor chip for X-Ray applications. I was also able to interview Dr. Turchetta to learn more about… Read More


EDA Tools to Optimize Memory Design

EDA Tools to Optimize Memory Design
by Daniel Payne on 06-21-2012 at 8:15 pm

I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they’ve expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more… Read More


Double Patterning Technology at DAC

Double Patterning Technology at DAC
by Daniel Payne on 06-20-2012 at 5:12 pm

David Abercrombie from Mentor Graphics met with me on Tuesday at DAC to provide an update on DPT – Double Patterning Technology, something new required for several layers starting at the 20nm node in order to get any IC yield. DPT is also part of Multiple-Patterning.… Read More


IPL Alliance at DAC

IPL Alliance at DAC
by Daniel Payne on 06-20-2012 at 3:25 pm

Lunch on Tuesday at DAC was sponsored by the IPL Alliance and thankfully this year they skipped the attempt at humor and focused on interoperable PDKs. Presenting companies include: Synopsys, Dongbu HiTek, TowerJazz, X-FAB and Si2. Having both OpenPDK and iPDK on the same platform does sound like a peaceful co-existence to me,… Read More


Atrenta Aquires NextOp

Atrenta Aquires NextOp
by Paul McLellan on 06-20-2012 at 10:00 am

Atrenta announced today that it is acquiring NextOp Software. NextOp sells a tool BugScope that provides assertion synthesis technology. This complements Atrenta’s SpyGlass products for improving the process for design of complex semiconductor IP and SoCs.

I went to Atrenta’s office to talk to Ajoy Bose (CEO)… Read More