At SemiWiki we’ve blogged before about 3D field solvers and the different approaches that trade off accuracy, speed and capacity:… Read More
Measuring the Accuracy of a 3D Field Solver for IC Extraction
Electronic Design Automation
A Brief History of EDA
Electronic Design Automation, or more affectionately known as EDA, is a relatively young $5B industry with a very colorful upbringing, one that I have experienced firsthand, I’m very grateful for, and is an honor to write about. Today EDA employs an estimated 27,000 people! There is a nice EDA Wikipedia page which can be found here… Read More
Synopsys Aquires Springsoft
Today it was announced that Synopsys is acquiring SpringSoft for $406 million dollars ($12.2B Taiwanese). Coincidentally, I was in SpringSoft’s US office yesterday to talk about how Laker is being used for 20nm design. More of that later. But there was certainly nothing to indicate that anyone there was expecting this.… Read More
Webinar on Multi-voltage/VT/Channel Length Libraries
Ken Brockof Synopsys presented on how to optimize your SoC design for low power at 40nm, 28nm and 20nm nodes in a webinar today. Ken and I both worked together at Silicon Compilers back in the late 1980’s, the best EDA/IP company that I’ve had the pleasure to join.
The webinar made a brief mention of 14nm and FinFETS but … Read More
Cadence Digital Flow
Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.
One of the tools in the Cadence… Read More
Schematic Capture and SPICE Simulation in the Cloud
In April I blogged about using the iPad for schematic capture and SPICE circuit simulation. My conclusion was that the technology was interesting but not quite ready for commercial use. Today I tried out the web-based version using my Google Chrome browser instead of the iPad. Install the Chrome app here or visit www.ischematic.com… Read More
The Unknown in Your Design Can be Dangerous
The SystemVerilog standard defines an X as an “unknown” value which is used to represent when simulation cannot definitely resolve a signal to a “1”, a “0”, or a “Z”. Synthesis, on the other hand, defines an X as a “don’t care”, enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often… Read More
Addressing the Nanometer Digital Design Challenges! (Webinars)
Optimizing logical, physical, electrical, and manufacturing effects, Cadence digital implementation technology eliminates iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start. … Read More
Synopsys Protocol Analyzer Video
Josefina Hobbs, a solutions architect at Synopsys, demonstrates protocol debug made easy using the Synopsys Protocol Analyzer. This gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. The video also shows the integration of Synopsys Protocol Analyzer with SpringSoft’s… Read More
Parasitic-Aware Design Flow with Virtuoso
I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot