CAST Compression IP Webinar 800x100 (2)
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A Brief History of Forte Design Systems

A Brief History of Forte Design Systems
by Daniel Nenni on 03-21-2013 at 8:10 pm

When Semiwiki readers see the name Forte Design Systems, they may think of the live bagpipers’ performance that closes the yearly Design Automation Conference. Forte has been the sponsor of this moving end to DAC since 2001. Step with me behind the plaid kilts for a good look at this remarkable company headquartered in San Jose, … Read More


Data Management for Designers

Data Management for Designers
by Paul McLellan on 03-21-2013 at 8:05 pm

Back when I was a programmer at VLSI Technology in the mid-1980s, I was responsible for all the data management in the VLSI Design Tools. By responsible for, I mean that I designed the whole system and wrote all the code. Prior to the 5th release of our product, there was no data management, designers simply used filenames and it was … Read More


View from the top: Brad Quinton

View from the top: Brad Quinton
by Daniel Payne on 03-20-2013 at 3:53 pm

Many engineers dream about starting their own company some day, and today I talked with an engineer that has gone beyond the dreaming stage to actually start an EDA company and then get that company acquired. His name is Brad Quinton and the start-up was called Veridae Systems, now part of Tektronix.


Brad QuintonRead More


Interconnect Optimization of an SoC Architecture

Interconnect Optimization of an SoC Architecture
by Daniel Payne on 03-20-2013 at 11:41 am

My last chip design at Intel was a GPU called the 82786and the architects of the chip wrote a virtual prototype using the MAINSAIL language. By using a virtual prototype they were able to:

  • Simulate bus traffic, video display and video RAM
  • Determine throughput
  • Measure latency
  • Verify that bus priorities were working
  • Optimize the
Read More

Wally Rhines, Victor Peng and Chenming Hu to Speak at Mentor User2User Conference

Wally Rhines, Victor Peng and Chenming Hu to Speak at Mentor User2User Conference
by glforte on 03-20-2013 at 10:29 am

This year’s Mentor Graphics user group meeting, User2User, will be held at the DoubleTree by Hilton in San Jose, California on April 25, 2013. The featured keynote presenters include…

  • Dr. Walden C. Rhines, CEO and Chairman of Mentor Graphics, talking about “Organizing by Design”
  • Victor Peng, Senior VP, Xilinx presenting on “The
Read More

A Brief History of Chips and Technologies

A Brief History of Chips and Technologies
by Paul McLellan on 03-19-2013 at 4:26 pm

I talked to Dado Banatao today. He is managing partner at Tallwood Venture Capital today but back in the mid-1980s he was the founder of Chips and Technologies, the first fabless semiconductor company. The rumors that they had a hard time raising money because VCs couldn’t comprehend a fabless semiconductor company are … Read More


RealTime Register Retiming

RealTime Register Retiming
by Paul McLellan on 03-19-2013 at 7:00 am

I was at the EDAC CEO forecast meeting last week and one of the questions that was asked of EDAC members was “which is the hottest EDA startup?” The one with the most nominations was Oasys. So Oasys is hot.

But register retiming is hotter.

The latest announcement from Oasys this morning is that register retiming is now … Read More


A tour of today’s Mixed-Signal solution

A tour of today’s Mixed-Signal solution
by Pawan Fangaria on 03-18-2013 at 10:00 pm


Mixed-Signal design is one of the very initial design methodologies, pioneered by Cadence with its lead in custom design; now taking centre space in the world of SoCs. Its growth is surmountable as it finds its place in most of the high growth electronics like smart phones, automotive applications, networks and communications,… Read More


Cadence IP Report Card 2013

Cadence IP Report Card 2013
by Daniel Nenni on 03-17-2013 at 7:00 pm

The challenges of developing IP blocks, integrating them correctly, and hitting the power, performance, area, and time to market requirements of a mobile SoC is a growing problem. At 20nm and 14nm the probability of a chip re-spin due to an error is approaching 50% and we all know how disastrous a re-spin can be, those are not good … Read More


Plotting to take over the time-domain only world

Plotting to take over the time-domain only world
by Don Dingee on 03-16-2013 at 10:00 am

The state machine nature of many digital designs has made time-domain debugging the favorite tool for most designers. We provide a set of inputs, data gets clocked in, and a set of outputs appears. We look for specific patterns in parallel paths, or sequences on serial lines.… Read More