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You can tune a piano, but you can’t tune a cache without help

You can tune a piano, but you can’t tune a cache without help
by Don Dingee on 05-30-2013 at 8:30 pm

Once upon a time, designing a product with a first generation SoC on board, we were trying to use two different I/O peripherals simultaneously. Seemed simple enough, but things just flat out didn’t work. After days spent on RTFM (re-reading the fine manual), we found ourselves at the absolute last resort: ask our FAE.

After about… Read More


SEMulator3D – A Virtual Fab Platform

SEMulator3D – A Virtual Fab Platform
by Pawan Fangaria on 05-30-2013 at 8:30 pm

Yes, it’s a pleasant surprise; it is Virtual Fabrication Platform, one of the new innovations in 2013. I was looking around for what kind of breakthrough technologies will be announced in DAC this year. And here I came across this new kind of innovative tool which can produce final virtual fabricated 3D structures after following… Read More


DAC lunch seminar: Better IP Test with IEEE P1687

DAC lunch seminar: Better IP Test with IEEE P1687
by Beth Martin on 05-30-2013 at 7:28 pm

What: DAC lunch seminar (register here)
When: June 5, 2013, 11:30am – 1:30pm
Where: At DAC in lovely Austin, TX

Dr. Martin Keim of Mentor Graphics will present this overview of the new the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG.

If you are involved in IC test*, you’ve probably heard about IJTAG. If you … Read More


TSMC ♥ Berkeley Design Automation

TSMC ♥ Berkeley Design Automation
by Daniel Nenni on 05-30-2013 at 11:00 am

As I mentioned in BDA Takes on FinFET Based Memories with AFS Mega:

Is AFS Mega real? Of course it is, I’m an SRAM guy and I worked with BDA on this product so I know. But don’t take my word for it, stay tuned for endorsements from the top SRAM suppliers around the world.

Here is the first customer endorsement from the #1 foundry.… Read More


Atrenta: Mentor/Spyglass Power Signoff…and a Book

Atrenta: Mentor/Spyglass Power Signoff…and a Book
by Paul McLellan on 05-30-2013 at 7:00 am

Today Atrenta and Mentor announced that they were collaborating to enable accurate, signoff quality power estimation at the RTL for entire SoCs. The idea is to facilitate RTL power estimation for designs of over 50M gates running actual software loads over hundreds of millions of cycles, resulting in simulation datasets in the… Read More


Advanced Verification – HW/SW Emulation – SoC/ASIC Prototyping

Advanced Verification – HW/SW Emulation – SoC/ASIC Prototyping
by Daniel Nenni on 05-29-2013 at 8:00 pm

market

Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. With an active user community of over 35,000, 50+ global partners, offices worldwide… Read More


Efficient Handling of Timing ECOs

Efficient Handling of Timing ECOs
by Daniel Nenni on 05-29-2013 at 8:00 pm

Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancing… Read More


The Hot Zone: Do Good While Having Fun

The Hot Zone: Do Good While Having Fun
by Paul McLellan on 05-29-2013 at 12:39 pm


The big 50th Anniversary party for DAC is on Monday night at the home of Austin City Limits. However, you can do good while enjoying yourself and also get into “The Hot Zone”, an exclusive area within the party in the penthouse Jack and Jim Gallery. The Gallery features 30 original photographs from the godfather of music… Read More


BDA Takes on FinFET-based Memories with AFS Mega

BDA Takes on FinFET-based Memories with AFS Mega
by Daniel Nenni on 05-29-2013 at 12:00 pm

Berkeley Design Automation today announced the first silicon-accurate circuit simulation for mega-scale arrays like memories and CMOS image sensors. If this tool lives up to its claims, it is going to be a big deal for FinFET-based circuits, Memory designers are rightly worried about having the accuracy necessary to include… Read More


RTL Signoff Theater

RTL Signoff Theater
by Paul McLellan on 05-29-2013 at 11:00 am

We have talked for years about RTL signoff, the idea that a design could be finalized at the RTL level and then most of the signoff would take place there. Then the design would be passed to a physical implementation team who would not expect to run into any problems (such as routing congestion, missing the power budget or similar problems).… Read More