ads mdx semiwiki building trust gen 800x100ai
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4278
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4278
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Mentor Teaches Us About the Higg’s Boson

Mentor Teaches Us About the Higg’s Boson
by Paul McLellan on 09-17-2013 at 4:46 pm
Categories: EDA, Siemens EDA

Once a year Mentor has a customer appreciation event in Silicon Valley with a guest speaker on some aspect of science. This is silicon valley, after all, so we all have to be geeks. This year it was Dr Sean Carroll from CalTech on The Particle at the End of the Universe, the Hunt for The Higg’s Boson and What’s Next.

Wally … Read More

Posted on

EDAC Export Seminar: Don’t Know This Stuff…Go Directly to Jail…Do Not Pass Go

EDAC Export Seminar: Don’t Know This Stuff…Go Directly to Jail…Do Not Pass Go
by Paul McLellan on 09-17-2013 at 2:04 pm
Categories: EDA

I am not making this up: All exports from the United States of EDA software and services are controlled under the Export Administration Regulations, administered by the U.S. Department of Commerce’s Bureau of Industry and Security (BIS). You need to understand these regulations. Failure to comply can result in severe … Read More

Posted on

How to Design an LTE Modem

How to Design an LTE Modem
by Paul McLellan on 09-16-2013 at 4:24 pm
Categories: EDA, Synopsys

Designing an LTE modem is an interesting case study in architectural and system level design because it is pretty much on the limit of what is possible in a current process node such as 28nm. I talked to Johannes Stahl of Synopsys about how you would accomplish this with the Synopsys suite of system level tools. He is the first to admit… Read More

Posted on

Analog Characterization Environment (ACE)

Analog Characterization Environment (ACE)
by Daniel Nenni on 09-12-2013 at 10:00 am
Categories: EDA, TSMC

I’m looking forward to the 2013 TSMC Open Innovation Platform Ecosystem Forum to be held Oct. 1[SUP]st[/SUP] in San Jose. One paper in particular that has my attention is titled, “An Efficient and Accurate Sign-Off Simulation Methodology for High-Performance CMOS Image Sensors,” by Berkeley Design Automation & … Read More

Posted on

Emerging Trend – Choose DRAM as per Your Design Need

Emerging Trend – Choose DRAM as per Your Design Need
by Pawan Fangaria on 09-11-2013 at 7:00 pm
Categories: Cadence, EDA

Lately I was studying about new innovations in memory world such as ReRAM and Memristor. As DRAM (although it has become a commodity) has found its extensive use in mobile, PC, tablet and so on, that was an inclination too to know more about. While reviewing Cadence’s offering in memory subsystems, I came across this whitepaperwhich… Read More

Posted on

Cadence Introduces Palladium XP II

Cadence Introduces Palladium XP II
by Paul McLellan on 09-09-2013 at 8:00 pm
Categories: Cadence, EDA

Well, despite all the arguments in the blogosphere about what process node palladium’s silicon is, and whether the design team is competent, and why it reports into sales…Cadence has announced their latest big revision of Palladium. Someone seems to be able to get things done. Of course it is bigger and faster and … Read More

Posted on

TSMC OIP: Mentor’s 5 Presentations

TSMC OIP: Mentor’s 5 Presentations
by Paul McLellan on 09-09-2013 at 6:30 pm
Categories: EDA, TSMC

At TSMC’s OIP on October 1st, Mentor Graphics have 5 different presentations. Collect the whole set!

11am, EDA track. Design Reliability with Calibre Smartfill and PERC. Muni Mohan of Broadcom and Jeff Wilson of Mentor. New methodologies were invented for 28nm for smart fill meeting DFM requirements (and at 20nm me may … Read More

Posted on

A Hybrid Test Approach – Combining ATPG and BIST

A Hybrid Test Approach – Combining ATPG and BIST
by Daniel Payne on 09-09-2013 at 5:18 pm
Categories: EDA

In the world of IC testability we tend to look at various approaches as independent means to an end, namely high test coverage with the minimum amount of test time, minimum area impact, minimum timing impact, and acceptable power use. Automatic Test Pattern Generation (ATPG) is a software-based approach that can be applied to any… Read More

Posted on

Verifying Hardware at the C-level

Verifying Hardware at the C-level
by Paul McLellan on 09-09-2013 at 2:25 pm
Categories: EDA

As more people adopt high-level synthesis (HLS) they start to worry about what is the best design flow to be using. This is especially so for verification since it forms such a large part of the effort on a modern SoC. The more people rely on HLS for producing their RTL from C, the more they realize they had better do a good job of verifying… Read More

Posted on

TSMC OIP: Soft Error Rate Analysis

TSMC OIP: Soft Error Rate Analysis
by Paul McLellan on 09-09-2013 at 1:34 pm
Categories: EDA, IROC Technologies, TSMC

Increasingly, end users in some markets are requiring soft error rate (SER) data. This is a measure of how resistant the design (library, chip, system) is to single event effects (SEE). These manifest themselves as SEU (upset), SET (transient), SEL (latch-up), SEFI (functional interrupt).

There are two main sources that cause… Read More