Banner Electrical Verification The invisible bottleneck in IC design updated 1
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SystemC: User Group update from DAC

SystemC: User Group update from DAC
by John Swan on 06-05-2014 at 12:00 pm

I always enjoy attending the SystemC User group to see what is being done by users of SystemC. This time was no exception. Not only is it FREE, but the professional networking around the meeting, presentations, and break times are terrific.

There were 5 paper presentations at the North American SystemC User Group (NASCUG) on Monday,… Read More


Synopsys Galaxy Platform & Lynx Design System supports FD-SOI

Synopsys Galaxy Platform & Lynx Design System supports FD-SOI
by Eric Esteve on 06-05-2014 at 11:36 am

This is a new brick that Synopsys brings to build FD-SOI credibility. We have talked at Semiwiki about FD-SOI technology developed by the LETI and STM, and recently endorsed by Samsung Foundry, offering a more than credible second source to STM. And we have said that the FD-SOI introduction will need to be supported by EDA and IP vendors… Read More


Non-separation of power and performance

Non-separation of power and performance
by Don Dingee on 06-04-2014 at 2:00 pm

How much power does a system consume? The simplistic path to power estimation for a system used to be tossing a few metrics – standby, typical, worst case, with figures pulled from a datasheet, simulation, or physical measurement – into a spreadsheet. After filling the remaining holes with SWAG (scientific wild-ass guesses), … Read More


IoT Breakfast Panel at DAC

IoT Breakfast Panel at DAC
by Daniel Payne on 06-03-2014 at 7:21 pm

Tuesday morning at DAC I enjoyed a free breakfast courtesy of Synopsysand GLOBALFOUNDRIESwhere I learned more about the emerging market of IoT, and what it means to semiconductor, EDA and IP vendors. Panelists included: Semico Research, HP, Synopsys, GLOBALFOUNDRIES and Broadcom. … Read More


Ceaseless Field Test for Safety Critical Devices

Ceaseless Field Test for Safety Critical Devices
by Pawan Fangaria on 06-03-2014 at 3:00 am

While focus of the semiconductor industry has shifted to DACin this week and unfortunately I couldn’t attend due to some of my management exams, in my spare time I was browsing through some of the webpages of Cadenceto check their new offerings (although they have a great list of items to showcase at DAC) and to my pleasure I came across… Read More


High Sigma Yield Analysis and Optimization at DAC

High Sigma Yield Analysis and Optimization at DAC
by Daniel Payne on 06-02-2014 at 7:20 pm

When I hear the phrase “high sigma” I think of the EDA vendor Solido, however at DAC on Monday I visited another EDA company called MunEDAthat has several products of interest to transistor-level IC designers. I was able to speak with three different people from MunEDA and here’s what I learned.… Read More


Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS

Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS
by Daniel Payne on 05-31-2014 at 9:20 pm

My former co-worker, Kenneth Bakalar at Mentor Graphics is an expert in AMS modeling languages and UPFmethodology, so he recently teamed up with Eric Jeandeau to author an interesting white paper: Interpreting UPF for a Mixed-Signal Design Under Test. This white paper is based on a presentation made at DVCon earlier this year.… Read More