CAST Compression IP Webinar 800x100 (2)
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EDA

Electronic Design Automation

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Synopsys Announces Verification Compiler

Synopsys Announces Verification Compiler
by Paul McLellan on 03-04-2014 at 8:00 am
Categories: EDA, Synopsys

Integration is often an underrated attribute of good tools, compared to raw performance and technology. But these days integration is differentiation (try telling that to your calculus teacher). Today at DVCon Synopsys announced Verification Compiler which integrates pretty much all of Synopsys’s verification technologies… Read More

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Does Multiprotocol-PHY IP really boost TTM?

Does Multiprotocol-PHY IP really boost TTM?
by Eric Esteve on 03-04-2014 at 4:33 am
Categories: IP, Synopsys

I have often written in Semiwiki about high speed PHY IP supporting Interface protocols (see for example this blog), the SoC cornerstone, almost as crucial as CPU, GPU or SDRAM Memory Controller. When you architect a SoC, you first select CPU(s) and/or GPU(s) to support the system basic functionality (Processor for Mobile application,… Read More

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Effect of Inductance on Interconnect

Effect of Inductance on Interconnect
by Daniel Nenni on 03-02-2014 at 11:00 am
Categories: EDA

In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for… Read More

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Locked on FPGA design brand recognition

Locked on FPGA design brand recognition
by Don Dingee on 02-28-2014 at 3:30 pm
Categories: Aldec, EDA, FPGA, Xilinx

Back in the days where computing was dominated by a few big (and now mostly dearly departed) names, there was a saying: “Nobody ever got fired for buying IBM.” The relative safety of immediate brand recognition, especially among non-technical upper management, dissuaded many users from recommending or even seeking out other … Read More

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Synopsys’s Next Generation Emulator, ZeBu Server-3

Synopsys’s Next Generation Emulator, ZeBu Server-3
by Paul McLellan on 02-28-2014 at 12:17 pm
Categories: EDA, Synopsys

Since Synopsys acquired Eve over a year ago, they haven’t announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new “release” is a complete re-design using new hardware fabric in a new process technology. Earlier… Read More

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Mixed-Signal SoC Debugging & IP Integration Made Easy

Mixed-Signal SoC Debugging & IP Integration Made Easy
by Pawan Fangaria on 02-28-2014 at 7:30 am
Categories: Concept Engineering, EDA

A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly.… Read More

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IoT: the sum of all technology opportunities

IoT: the sum of all technology opportunities
by Don Dingee on 02-26-2014 at 5:00 pm
Categories: EDA

There was a time not that long ago, before smartphones arrived on the scene, where Mentor Embedded Nucleus RTOS was dominant in non-Nokia feature phones – Mentor is part of the “Billion Unit Mobile Club”. Since then, Mentor has been searching to recreate that type of success, and like so many other software firms, they are now aiming… Read More

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TI’s Way of Strategies – Formation & Execution

TI’s Way of Strategies – Formation & Execution
by Pawan Fangaria on 02-26-2014 at 8:30 am
Categories: EDA, Foundries, General

For a company to stand still and continually prosper even after facing several downturns in its career of 80+ years, and still move swiftly with strong commitment and confidence, its strategy has to be right and rock solid possessing sustainable competitive advantage, and of course it has to be an early mover in everything it does… Read More

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A Brief History of Chip Design at Apple Computer

A Brief History of Chip Design at Apple Computer
by Daniel Payne on 02-25-2014 at 9:36 pm
Categories: EDA

Steve Wozniak in 1976 designed the Apple 1 while working at HP during the daytime, and he used standard parts to keep costs low, like:

  • 6502 CPU from MOS Technology
  • 8K of DRAM
  • TTL logic for driving video and random logic
  • PROM to hold the BASIC language and primitive OS
… Read More
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SoC Functional Verification Planning and Management Goes Big

SoC Functional Verification Planning and Management Goes Big
by Daniel Payne on 02-24-2014 at 10:01 am
Categories: Cadence, EDA

Big SoC designs typically break existing EDA tools and old methodologies, which then give rise to new EDA tools and methodologies out of necessity. Such is the case with the daunting task of verification planning and management where terabytes of data have simply swamped older EDA tools, making them unpleasant and ineffective… Read More