Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Standard Cell, IO and Hard IP Validation update

Standard Cell, IO and Hard IP Validation update
by Daniel Payne on 06-27-2014 at 1:26 pm
Categories: EDA, Fractal Technologies

Every SoC team uses libraries of cells to get their new product to market quicker: Standard Cells, IO Cells and Hard IP blocks. One immediate question that comes to my mind is, “How clean are these cells?” Validating your cell libraries first makes sense, and will ensure that there are fewer surprises as your chip gets… Read More

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IP Management Update at DAC

IP Management Update at DAC
by Daniel Payne on 06-26-2014 at 12:42 pm
Categories: EDA, Perforce

To keep track of my business and personal finances I use software from Quicken, but for an SoC with hundreds of IP blocks how do you keep track of everything? The answer is found in the growing field of EDA tools for IP management, and at DACearlier this month I sat down with Neil Handof Methodics to get an update on what the industry trends… Read More

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What’s New with Circuit Simulation for Cadence?

What’s New with Circuit Simulation for Cadence?
by Daniel Payne on 06-26-2014 at 11:53 am
Categories: Cadence, EDA

Every year at DAC I enjoy making the rounds to see what’s new with SPICE circuit simulators, so on June 3rd I met with Xiuya Liand Dan Zhuof Cadence in San Francisco to get an update about their Spectre tool. There’s plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys … Read More

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Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am
Categories: Aldec, EDA, FPGA

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot… Read More

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Single Event Upsets

Single Event Upsets
by admin on 06-25-2014 at 5:04 pm
Categories: EDA

Do you know what a SEE is? It stands for single event upset. We live on a radioactive planet which is also bombarded with cosmic rays, so particles are bombarding our chips. The materials used in packaging also can create particles that cause problems, even the solder. Reliability and aging has been an area that has not been at the forefront… Read More

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Wally Rhines at #51DAC: EDA Grows From Solving New Problems

Wally Rhines at #51DAC: EDA Grows From Solving New Problems
by Paul McLellan on 06-24-2014 at 8:23 pm
Categories: EDA, Siemens EDA

Wally Rhines gave the keynote at DAC in 2004. One of the things that he pointed out ten years ago was that EDA revenue for any given market segment is pretty much flat once the initial growth phase has taken place and the market has been established. Incremental EDA revenue only comes from delivering new capabilities. Historically… Read More

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The Secret Essence of an IoT Design

The Secret Essence of an IoT Design
by Pawan Fangaria on 06-23-2014 at 7:00 am
Categories: EDA

Today the semiconductor industry along with electronics industry is looking up to capitalize from massive expansion foreseen in IoT (Internet of Things) domain. In simple terms we can consider IoT as connectivity between machines which can communicate with each other and work as programmed. In localized applications such … Read More

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Intel Invests in the Fabless Ecosystem!

Intel Invests in the Fabless Ecosystem!
by Daniel Nenni on 06-22-2014 at 11:00 am
Categories: Ansys, Inc., Cadence, EDA, Intel Foundry, Siemens EDA, Synopsys

During my illustrious career one of the most useful axioms that I use just about everyday day is: “Understand what people say but also understand why they are saying it.” This certainly applies to press releases so let’s take a look at what Intel unleashed during #51DAC (in alphabetical order):

ANSYS And Intel Collaborate… Read More

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ARC EM DSP supports Always-on Devices

ARC EM DSP supports Always-on Devices
by Eric Esteve on 06-22-2014 at 3:01 am
Categories: IP, Synopsys

The ARC EM family is the low-power, embedded and low footprint processor part of the larger ARC processor. To target the ultra low-power markets like wearable and IoT, Synopsys has added DSP capabilities to EM5D and EM7D. To be specific, these cores are optimized for ultra low-power control and DSP, thanks to:

  • Energy-efficient
… Read More