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EDA

Electronic Design Automation

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Temperature – The Fourth Aspect to Look at in SoC Design

Temperature – The Fourth Aspect to Look at in SoC Design
by Pawan Fangaria on 07-25-2014 at 2:00 pm
Categories: EDA, Siemens EDA, TSMC

In my career in semiconductor industry, I can recall, in the beginning there was emphasis on design completion with automation as fast as possible. The primary considerations were area and speed of completion of a semiconductor design. Today, with unprecedented increase in multiple functions on the same chip and density of the… Read More

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Hybrid Emulation

Hybrid Emulation
by Paul McLellan on 07-25-2014 at 9:01 am
Categories: EDA, Synopsys

Hybrid emulation is when part of the system is run in the emulator and part of the system is run in a virtual prototype. Typically a model of the processor(s) is run in the virtual platform and then the rest of the design is modeled by running the RTL on the emulator. I talked to Tom Borgstrom at Synopsys about what technology they have … Read More

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Power Modeling and Simulation of System Memory Subsystem

Power Modeling and Simulation of System Memory Subsystem
by Daniel Payne on 07-24-2014 at 11:05 am
Categories: EDA

One great benefit of designing at the ESL level is the promise of power savings on the order of 40% to 70% compared to using an RTL approach. Since a typical SoC can contain a hierarchy of memory, this kind of power savings could be a critical factor in meeting PPA goals. To find out how an SoC designer could use such an ESL approach to power… Read More

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Cadence Results: Good but Palladium under Price Pressure

Cadence Results: Good but Palladium under Price Pressure
by Paul McLellan on 07-21-2014 at 10:00 pm
Categories: Cadence, EDA

Cadence announced their 2Q results this afternoon. I listened to the conference call.

You can read all the details of the results in the press release but the big picture is:

  • Revenue $379K, net income $23M GAAP or $64M non-GAAP (8, 21c per share, beat estimates by 1c). Equivalent quarter last year was $362M so less than 5% increase)
… Read More
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Intel vs AMD

Intel vs AMD
by Daniel Nenni on 07-21-2014 at 6:00 pm
Categories: EDA, Foundries

While listening to the Intel and AMD conference calls last week I was reminded of the ATI acquisition by AMD and the painfully long cultural assimilation that ensued. The title of this blog could just as easily have been “Custom vs Synthesizable Design Cultures” or “The Real Reason Why AMD is Fabless” because that is closer to how … Read More

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When is a Million-Year MTBF Too Short?

When is a Million-Year MTBF Too Short?
by Jerry Cox on 07-21-2014 at 8:00 am
Categories: EDA

The reliability metric, Mean Time Between Failures (MTBF), is often misunderstood. Use of an MTBF metric generally assumes a random failure process, one that is very infrequent and has no memory of past failures. Such failure modes can occur in System-on-Chip (SoC) designs and include radiation effects, synchronizer malfunctions… Read More

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New Release of Semulator3D at #semiconwest

New Release of Semulator3D at #semiconwest
by Paul McLellan on 07-19-2014 at 9:01 am
Categories: Coventor, EDA

One of Coventor’s flagship products is SEMulator3D, and at Semicon West they announced a new version, 2014.100.

SEMulator3D is a powerful 3D semiconductor and MEMS process modeling platform. It uses highly efficient physics-driven voxel modeling technology. It models the physical effects of process steps, which is… Read More

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Winds of Change in the Custom Chip Market

Winds of Change in the Custom Chip Market
by Peter Gasperini on 07-18-2014 at 4:00 pm
Categories: EDA

The most interesting part of the semiconductor market for me has always been the Custom Chip sector – the FPGA, ASIC and SoC companies where I have spent my entire career. These three segments provide an excellent barometer of the overall state of financial health and technological innovation for the entire High Tech industry, … Read More

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Palladium’s Little Brother Protium

Palladium’s Little Brother Protium
by Paul McLellan on 07-17-2014 at 8:00 am
Categories: Cadence, EDA

Today, Cadence announced Protium, a new FPGA prototyping platform for software development. During development of an SoC, the most appropriate methodology changes. In the early days, developing RTL, the primary tool is simulation. Then, as the blocks get bigger or as the whole chip starts to come together, typically simulation… Read More

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Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing

Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing
by Daniel Payne on 07-16-2014 at 3:00 pm
Categories: EDA, Synopsys

Test engineers are often the unsung heroes in the semiconductor world, because they have the tough job of deciding if each IC is good or bad, while taking the least amount of time on a tester and ensuring that the tests are actually finding and uncovering all manufacturing and process variation defects. Simple stuck-at fault models… Read More