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IC/Package/Board – Power, Noise and Reliability from ANSYS (Apache DA) at DAC

IC/Package/Board – Power, Noise and Reliability from ANSYS (Apache DA) at DAC
by Daniel Payne on 04-30-2014 at 10:04 am

ANSYS acquired Apache Design Automation back in June 2011and three years later the name “Apache” is being subdued in favor of using just ANSYS. One thing that I noticed right away was a DACfocus on having actual ANSYS customers talk about their hands-on experience using the EDA tools. The following seven customers… Read More


An AMS and RF IC Design Flow

An AMS and RF IC Design Flow
by Daniel Payne on 04-30-2014 at 1:24 am

The big three in EDA are well-know for offering AMS and RF IC design flows, but today you also have alternative EDA vendors available that have capable tools, yet are lessor known. This blog will present an overview of the AMS and RF IC design flowoffered by Silvaco, an EDA company with a strong history in TCAD tools like Utmost IV for… Read More


Designing Change into Semiconductor Techonomics

Designing Change into Semiconductor Techonomics
by Daniel Payne on 04-29-2014 at 5:23 pm

Every industry has famous thought leaders that can summarize where we’ve been and then paint a picture of where we’re headed towards in the future. Often they make statements that become industry expressions, like “Moore’s Law” or the “Internet of Things”. I think that if Synopsys… Read More


More knowledge, less time in FPGA-based prototyping

More knowledge, less time in FPGA-based prototyping
by Don Dingee on 04-29-2014 at 4:00 pm

I recently published a post on LinkedIn titled “Sometimes, you gotta throw it all out” in reference to the innovation process and getting beyond good to better. A prime example has crossed my desk: the new ProtoCompiler software for Synopsys HAPS FPGA-based prototyping systems.

Last week, I spoke with Troy Scott, product marketing… Read More


Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance

Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance
by Daniel Nenni on 04-29-2014 at 10:00 am

Tanner EDA is making waves at their customer’s sites as the mixed-signal design suite from Tanner EDA, Incentia Design Systems, Inc. and Aldec, Inc. helps ASIC Design House lower cost and increase efficiency with no compromise in performance. In today’s ‘always on’, Internet of Things connected world, the demand for high-performance,… Read More


Carey Robertson: Reliability Checks in Advanced Nodes

Carey Robertson: Reliability Checks in Advanced Nodes
by Daniel Nenni on 04-28-2014 at 8:30 pm

Last week I had the pleasure of presenting at the Electronic Design Process Symposium (EDPS) workshop. This was my first time attending and I was very impressed. There were good presentations but I learned as much from the Q&A and the side conversations before/after/breakfast/lunch/etc. If you have the opportunity to attend,… Read More


FinFET & Multi-patterning Need Special P&R Handling

FinFET & Multi-patterning Need Special P&R Handling
by Pawan Fangaria on 04-28-2014 at 1:00 pm

I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More


Dr. Bernard Murphy: My presentation at EDPS 2014

Dr. Bernard Murphy: My presentation at EDPS 2014
by Daniel Nenni on 04-28-2014 at 8:00 am

First, I wish there were more conferences/workshops like this. This is much more about sharing ideas and brainstorming than the stark commercialism of DAC. I presented Atrenta’s role in enabling 3[SUP]rd[/SUP]-party IP qualification for the TSMC soft IP library.

My presentation slides are located here:

http://www.eda.org/edps/Papers/5-3%20Bernard%20Murphy.pdfRead More


Secret of TI’s Success in Analog & Embedded Space

Secret of TI’s Success in Analog & Embedded Space
by Pawan Fangaria on 04-27-2014 at 7:30 am

Since I started looking at the ways Texas Instrumentsworks through its strategies, my belief is getting firmed up that this is one company which can always sail through rough waters during downturn and reap rich benefits during upturn. They regularly review their strategies and can predict ahead of time when the water is about … Read More


Webinar: Making Design Reuse Work

Webinar: Making Design Reuse Work
by Daniel Nenni on 04-26-2014 at 9:00 pm

Please join me for an IP conversation in collaboration with ClioSoft on Wednesday, April 30th, 2014 @ 11:00 AM PST. At the EDPS Workshop IP day there were two interesting presentations on IP reuse. The first one was by Warren Savage of IPextreme: Top Ten Reasons Why Internal IP Reuse Fails. The second was by Ranjit Adhikary of ClioSoft:… Read More