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EDA

Electronic Design Automation

Podcast EP349: llmda.a’s Unique AI Fabric for Embedded Systems Development with Nagesh Gupta

Podcast EP349: llmda.a’s Unique AI Fabric for Embedded Systems Development with Nagesh Gupta
by Daniel Nenni on 06-05-2026 at 10:00 am
Categories: AI, EDA, llmda.ai

Daniel is joined by Nagesh Gupta, CEO of llmda.ai. Nagesh has built a career spanning multiple aspects of system design and development at companies including Hewlett-Packard, Cadence, Xilinx, and Lattice Semiconductor. He is also a serial entrepreneur. Nagesh founded Taray, Inc., which developed memory interface generators… Read More

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Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools

Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
by Daniel Nenni on 06-04-2026 at 6:00 am
Categories: 3D IC, Chiplet, EDA, Foundries, Intel Foundry, IP, Synopsys
4 Comments

synopsys intel linkedin update 1200x1200 v3

As advanced packaging becomes a critical enabler for next-generation semiconductor products, Intel continues to drive innovation through its Embedded Multi-die Interconnect Bridge (EMIB) technology. EMIB has emerged as a foundational packaging solution for heterogeneous integration, allowing multiple chiplets and… Read More

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Convergence Evidence Maturity Hierarchy: From Raw Data to Convergence-Authoritative Evidence

Convergence Evidence Maturity Hierarchy: From Raw Data to Convergence-Authoritative Evidence
by Moh Kolb on 06-03-2026 at 8:00 am
Categories: 3D IC, Chiplet, EDA

Picture1 CEMH

The semiconductor industry is generating more engineering data than ever before.

This article follows the previously published GFL and TCG foundation pieces. GFL introduced the lifecycle-governance problem. TCG clarified why observable or interoperable data is not automatically trustworthy convergence evidence. CEMH… Read More

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An Update on IP Lifecycle Management (IPLM)

An Update on IP Lifecycle Management (IPLM)
by Bernard Murphy on 06-03-2026 at 6:00 am
Categories: AI, EDA, Perforce

IP Lifecycle Management

IPLM is not always prominent, nevertheless it is a very necessary aspect of semiconductor (and systems) design. Modern designs build on a wide range of IPs and subsystems, each evolving through multiple variants and versions, each with different PPA characteristics and recommended use-cases, many from different suppliers… Read More

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Learn How llmda Uses Agentic AI to Generate Hardware Docs & Keep Them Consistent

Learn How llmda Uses Agentic AI to Generate Hardware Docs & Keep Them Consistent
by Mike Gianfagna on 06-02-2026 at 8:00 am
Categories: AI, EDA, llmda.ai

If You Struggle with Up To Date Documentation llmda.ai Can Help

Accurate, complete, and consistent technical documentation is a critical element of success for any embedded system design project. This includes IP, SoCs, and the associated hardware and software infrastructure. When documentation contains errors, the consequences go beyond engineering inefficiency. Errors that drive… Read More

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Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P

Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P
by Daniel Nenni on 06-01-2026 at 6:00 am
Categories: IP, Mixel, Silvaco, TSMC

Mixel MIPI 2026

The transition to advanced process nodes is reshaping high-speed interface IP requirements for mobile, automotive, AR/VR, and AI edge devices. As SoC designers migrate to cutting-edge foundry technologies, the demand for highly optimized MIPI PHY solutions continues to grow. A key development in this space is the availability… Read More

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The Hidden Cost of Using Claude for Documentation

The Hidden Cost of Using Claude for Documentation
by Mike Gianfagna on 05-29-2026 at 8:00 am
Categories: AI, EDA, llmda.ai

Why Generic LLMs Fall Short for Critical Engineering Documentation

Engineering documentation has always been difficult to produce, maintain, and scale. But with the rise of generative AI, many organizations are asking a reasonable question: can a general-purpose large language model (LLM) like Claude automate the work? At first glance, the answer appears to be yes.

Modern LLMs can generate… Read More

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SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability

SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
by Admin on 05-27-2026 at 10:00 am
Categories: Defacto Technologies, EDA
1 Comment

Defacto SoC Planner

With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.

Indeed, for a complex SoC project, the number of possible configurations… Read More

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Engineering the Next Era of Semiconductor Innovation

Engineering the Next Era of Semiconductor Innovation
by Kalar Rajendiran on 05-27-2026 at 8:00 am
Categories: 3D IC, AI, Chiplet, EDA, Siemens EDA

Da Yang U2UNA2026 77

The semiconductor industry is entering a transformative new phase, driven by the convergence of artificial intelligence, cloud computing, and increasingly complex chip architectures. That message took center stage during the keynote talks at the Siemens EDA User2User 2026 North America conference. Executives from Siemens,… Read More

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SRAM compilers targeting automotive SoCs on advanced nodes

SRAM compilers targeting automotive SoCs on advanced nodes
by Don Dingee on 05-27-2026 at 6:00 am
Categories: IP, Synopsys

Automotive versus consumer grade reliability

Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More