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The Growing Importance of PVT Monitoring for Silicon Lifecycle Management

The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
by Kalar Rajendiran on 04-24-2025 at 6:00 am

SLM IP Target Applications

In an era defined by complex chip architectures, ever-shrinking technology nodes and very demanding applications, Silicon Lifecycle Management (SLM) has become a foundational strategy for optimizing performance, reliability, and efficiency across the lifespan of a semiconductor device. Central to effective SLM are Process,… Read More


Perspectives from Cadence on Data Center Challenges and Trends

Perspectives from Cadence on Data Center Challenges and Trends
by Bernard Murphy on 04-23-2025 at 6:00 am

Cadence Data Center Report Image

From my vantage point in the EDA foxhole it can be easy to forget that Cadence also has interests in much broader technology domains. One of these is in data center modeling and optimization, through their Cadence Reality Digital Twin Platform. This is an area in which they already have significant track record collaborating with… Read More


Designing and Simulating Next Generation Data Centers and AI Factories

Designing and Simulating Next Generation Data Centers and AI Factories
by Kalar Rajendiran on 04-22-2025 at 10:00 am

Digital Twin and the AI Factory Lifecycle

At NVIDIA’s recent GTC conference, a Cadence-NVIDIA joint session provided insights into how AI-powered innovation is reshaping the future of data center infrastructure. Led by Kourosh Nemati, Senior Data Center Cooling and Infrastructure Engineer from NVIDIA and Sherman Ikemoto, Sales Development Group Director from … Read More


Verifying Leakage Across Power Domains

Verifying Leakage Across Power Domains
by Daniel Payne on 04-21-2025 at 10:00 am

leakage contention

IC designs need to operate reliably under varying conditions and avoid inefficiencies like leakage across power domains. But how do you verify that connections between IP blocks has been done properly? This is where reliability verification, Electrical Rule Checking (ERC) tools and dynamic simulations all come into play particularly… Read More


How Cadence is Building the Physical Infrastructure of the AI Era

How Cadence is Building the Physical Infrastructure of the AI Era
by Kalar Rajendiran on 04-21-2025 at 6:00 am

Phases of AI Adoption

At the 2025 NVIDIA GTC Conference, CEO Jensen Huang delivered a sweeping keynote that painted the future of computing in bold strokes: a world powered by AI factories, built on accelerated computing, and driven by agentic, embodied AI capable of interacting with the physical world. He introduced the concept of Physical AI—intelligence… Read More


Achieving Seamless 1.6 Tbps Interoperability for High BW HPC AI/ML SoCs: A Technical Webinar with Samtec and Synopsys

Achieving Seamless 1.6 Tbps Interoperability for High BW HPC AI/ML SoCs: A Technical Webinar with Samtec and Synopsys
by Daniel Nenni on 04-17-2025 at 10:00 am

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HPC Bandwidth Explosion and 1.6T Ecosystem Interop Need

The exponential growth in data bandwidth requirements driven by HPC systems, AI, and ML applications has set the stage for an ever-increasing need for 1.6Tbps Ethernet. As data centers strive to manage vast data transfers with maximum efficiency, the urgency for interoperability… Read More


SNUG 2025: A Watershed Moment for EDA – Part 1

SNUG 2025: A Watershed Moment for EDA – Part 1
by Lauro Rizzatti on 04-15-2025 at 6:00 am

SNUG 2025 A Watershed Moment for EDA Figure 1

Hot on the heels of DVConUS 2025, the 35th annual Synopsys User Group (SNUG) Conference made its mark as a defining moment in the evolution of Synopsys—and the broader electronic design automation (EDA) industry. This year’s milestone event not only underscored Synopsys’ continued innovation but also affirmed the vision… Read More


Balancing the Demands of OTP for Advanced Nodes with Synopsys IP

Balancing the Demands of OTP for Advanced Nodes with Synopsys IP
by Mike Gianfagna on 04-14-2025 at 6:00 am

Balancing the Demands of OTP for Advanced Nodes with Synopsys IP

One-time programmable (OTP) non-volatile memory has been around for a long time. Compared to other non-volatile memory technologies OTP has a smaller footprint and does not require additional manufacturing steps, making it a popular choice to store items such as boot code and encryption keys. While this sounds simple, the growth… Read More


Synopsys Webinar: The Importance of Security in Multi-Die Designs – Navigating the Complex Landscape

Synopsys Webinar: The Importance of Security in Multi-Die Designs – Navigating the Complex Landscape
by Daniel Nenni on 04-11-2025 at 6:00 am

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In today’s rapidly evolving digital landscape, the security of electronic systems is of the highest priority. This importance is underscored by technological advancements and increasing regulatory demands. Multi-die designs which integrate multiple dies (also called chiplets) into a single package, introduce … Read More


Generative AI Comes to High-Level Design

Generative AI Comes to High-Level Design
by Daniel Payne on 04-10-2025 at 10:00 am

high level agents min

I’ve watched the EDA industry change the level of design abstraction starting from transistor-level to gate-level, then RTL, and finally using High Level Synthesis (HLS). Another emerging software trend is the use of generative AI to make coding RTL more automated. There’s a new EDA company called Rise Design Automation that… Read More