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What is Inside of the Samsung Galaxy S6?

What is Inside of the Samsung Galaxy S6?
by Daniel Payne on 04-06-2015 at 1:00 pm

I’ve always been curious about what is inside an electronic device, and it was seeing the very first TI handheld calculator that got me started into a career as an Electrical Engineer. Next to Apple, the most popular brand in smart phone devices these days has got to be Samsung and they have just launched the Galaxy S6 device.… Read More


Security All Around in SoCs at DAC

Security All Around in SoCs at DAC
by Pawan Fangaria on 04-06-2015 at 12:00 am

Last month I was on my way to write a detailed article on important aspects to look at while designing an SoC. This was important in the new context of modern SoCs that go much beyond the traditional power, performance and area (PPA) requirements. I had about 12-13 parameters in my list that I couldn’t cover in one go, so I put the write-up… Read More


The Changing Foundry Landscape: Trends and Challenges!

The Changing Foundry Landscape: Trends and Challenges!
by Daniel Nenni on 04-05-2015 at 4:00 am

This will be a year of change for the fabless semiconductor ecosystem, absolutely. Last year we were wondering how Samsung Mobile was going to compete with the China clones and other low end smart phones. We now know the answer to that question thanks to the Chipworks tear down of the Galaxy S6. SemiWiki IP expert Dr. Eric Esteve blogged… Read More


Variation Alphabet Soup

Variation Alphabet Soup
by Paul McLellan on 04-04-2015 at 1:00 pm

On-chip variation (OCV) is a major issue in timing signoff, especially at low voltages or in 20/16/14nm processes. For example, the graph below shows a 20nm inverter. At 0.6V the inverter has a delay of 2 (nominalized) units. But due to on-chip variation this might be as low as 1.5 units or as high as 3 units, which is a difference from… Read More


DAC Keynotes: Mark Your Calendar

DAC Keynotes: Mark Your Calendar
by Paul McLellan on 04-03-2015 at 7:00 am

DAC starts in San Francisco on June 8th. The kickoff keynote at 9.20am that morning is by Brian Otis of Google. He is a director at Google[x]. According to Wikipedia:Google X, stylized as Google[x], is a semi-secret facility run by Google dedicated to making major technological advancements. It is located about a half mile from Read More


ANSYS Event to Highlight Cutting Edge Technology Development

ANSYS Event to Highlight Cutting Edge Technology Development
by Tom Simon on 04-02-2015 at 5:00 pm

If you follow technology news, it would be hard to deny that we live in exciting times. In some ways there is an unparalleled amount of big and cool technology development going on right now. We all have followed the rise of Tesla Motors. They took over a long vacant US big-auto plant in Fremont and are reinventing the US automobile industry.… Read More


EDPS: Fins and FinFETs

EDPS: Fins and FinFETs
by Paul McLellan on 04-02-2015 at 7:00 am

Look at those dolphins with fins on their backs. Did you know that FinFETs are actually named after them since Chenming Hu and his team though that they looked like a fish’s fin? And since they invented FinFETs they got to name them too. But those dolphins also mean that it is nearly time for this years Electronic Design Process… Read More


What is Skipper?

What is Skipper?
by Paul McLellan on 04-01-2015 at 1:00 am

What is Skipper? Well, it seems it’s a penguin in the movie Madagascar. And one of Barbie’s sisters. Who knew? But for Semiwiki readers it’s an integrated chip finishing platform from ICScape. Skipper can read in full-chip layout extremely fast, examine it and manipulate it in various ways, and write it out again.… Read More


Secret Sauce for Successful Mixed-signal SoCs

Secret Sauce for Successful Mixed-signal SoCs
by admin on 03-31-2015 at 12:00 pm

For a design engineer engulfed in the daily rigorous routine of having to keep in sync with updates from various design team members as well the dictums of the design management team, the task of remaining up-to-date with the design information is very often daunting.

What design changes have been checked in this week? Is the verification… Read More


Verifying the RTL Coming out of a High-Level Synthesis Tool

Verifying the RTL Coming out of a High-Level Synthesis Tool
by Daniel Payne on 03-30-2015 at 9:30 pm

With High-Level Synthesis (HLS) the first benefit that comes to my mind is reduced design time, because coding with C or SystemC is more efficient than low-level RTL code. What I’ve just learned is that there’s another benefit, a reduction in the amount of functional simulation required. One HLS customer was able … Read More