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EDA

Electronic Design Automation

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Dr. Walden Rhines on the Past Present and Future!

Dr. Walden Rhines on the Past Present and Future!
by Daniel Nenni on 03-06-2016 at 7:00 am
Categories: EDA, Siemens EDA

Who can present seventy six slides in sixty minutes, still have time for questions, AND make it interesting? Dr. Walden Rhines that’s who. Here is a link to the presentation but I have to warn you, it is a 100MB PDF file:

Design Verification Challenges: Past, Present, and Future

The DVCon conference was well attended again this year… Read More

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A Brief History of Defacto Technologies

A Brief History of Defacto Technologies
by Pawan Fangaria on 03-04-2016 at 7:00 am
Categories: Defacto Technologies, EDA

In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes… Read More

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Solving the Next Big SoC Challenges with FPGA Prototyping

Solving the Next Big SoC Challenges with FPGA Prototyping
by Daniel Nenni on 03-01-2016 at 4:00 pm
Categories: EDA, FPGA, S2C EDA

The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If… Read More

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Multi-Level Debugging Made Easy for SoC Development

Multi-Level Debugging Made Easy for SoC Development
by Pawan Fangaria on 03-01-2016 at 7:00 am
Categories: Concept Engineering, EDA

An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.… Read More

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FPGA tools for more predictive needs in critical

FPGA tools for more predictive needs in critical
by Don Dingee on 02-29-2016 at 4:00 pm
Categories: Blue Pearl Software, EDA, FPGA

“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when?… Read More

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Reinventing Power Management ICs for Mobile

Reinventing Power Management ICs for Mobile
by Karim Khalfan on 02-29-2016 at 7:00 am
Categories: Cliosoft, EDA

Semiconductor startups are becoming rather rare in Silicon Valley, otherwise known as the cradle of technology innovation. In an era where social media and cloud-based software startups are sprouting in every nook and corner of the Valley, it is extremely difficult to get venture capital funding for semiconductor startups,… Read More

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HW Emulator Apps Open Doors to Entirely New Uses

HW Emulator Apps Open Doors to Entirely New Uses
by Tom Simon on 02-28-2016 at 7:00 am
Categories: EDA, Siemens EDA

When the topic of hardware emulation comes up, thoughts of big iron customarily come to mind. However, hardware emulation has evolved significantly and now there are other important traits that distinguish the offerings in this area. For a very long period of time emulators provided primarily a method to accelerate gate level… Read More

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Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA, Prototyping

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping.… Read More

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HW/SW Interfaces for Portable Stimulus

HW/SW Interfaces for Portable Stimulus
by Pawan Fangaria on 02-26-2016 at 12:00 pm
Categories: EDA

With growing size and complexity of SoC, the semiconductor community is realizing the growing pain of verification. The cost of SoC verification grows exponentially with design size. Moreover, there is no single methodology for verifying a SoC; multiple engines are used in different contexts through different verification… Read More