Banner Electrical Verification The invisible bottleneck in IC design updated 1
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What’s The Significance Of Applied Micro’s X-Gene 3 And X-Tend Interconnect?

What’s The Significance Of Applied Micro’s X-Gene 3 And X-Tend Interconnect?
by Patrick Moorhead on 01-10-2016 at 4:00 pm

The void left by the Advanced Micro Devices X86 server chip “sabbatical” five years ago created a massive opportunity in the server SoC space. It had to be filled with something and that something has primarily been Intel and then ARM-based server chips. ARM Holdings -based servers have been in development for years now and the ecosystem… Read More


Doubling of qubits, Superconducting States and Law for Quantum Computing!

Doubling of qubits, Superconducting States and Law for Quantum Computing!
by Vaibbhav Taraate on 01-07-2016 at 4:00 pm

If we consider the miniaturization era from year 1963 to 2014 then the computing power of classical computer has increased multi-fold and with the increasing growth in the computing power for every two years the cost per chip has dropped exponentially from few million dollar to few dollars, or even less than dollar per chip. The … Read More


IP Development in Japan

IP Development in Japan
by Pawan Fangaria on 01-07-2016 at 12:00 pm

As semiconductor IP is growing bigger in size and more complex in providing complete solution for a particular functionality in an SoC, regions from across the world are joining to provide various types of services in the overall value-chain of IP development, verification, and its integration into SoCs. … Read More


EDA and the Big Short!

EDA and the Big Short!
by Daniel Nenni on 01-05-2016 at 8:00 pm

A funny thing happened while I was reading “The Big Short: Inside the Doomsday Machine”. The book explains the subprime mortgage crisis in painful detail by profiling several key players who predicted and profited from the bubble pop. As a home owner and faux slumlord I had a front row seat to this horror show so it was an interesting… Read More


Semiconductors Future Hinges on a Single Pillar

Semiconductors Future Hinges on a Single Pillar
by Pawan Fangaria on 01-03-2016 at 7:00 am

A unique phenomenon has started manifesting itself under the slew of mergers and acquisitions this year in the semiconductor landscape. This phenomenon is bound to intensify in the near future and would positions itself as a key factor for the future of the semiconductor industry. The winners and losers in the game would be determined… Read More


The “Era of the Photon” is here!

The “Era of the Photon” is here!
by Tom Dillinger on 01-02-2016 at 12:00 pm

The 50 year anniversary of the publication of Moore’s Law was recently celebrated, highlighting the tremendous advances in the Microelectronics Eraof the period in human history known as the Information Age. However, the technical and economic challenges currently faced by the microelectronics industry are bringing into… Read More


MediaTek X20 Benchmark Leaks: A Prelude to 2016 Mobile Chipset Wars?

MediaTek X20 Benchmark Leaks: A Prelude to 2016 Mobile Chipset Wars?
by Majeed Ahmad on 01-02-2016 at 7:00 am

MediaTek is making waves, again. The company’s flagship mobile system-on-chip (SoC)—Helio X20—is up against rivals like Apple, Qualcomm and Samsung, according to leaked Geekbench scores, and is leading in some of the performance benchmarks.… Read More


How Not To Be Incoherent

How Not To Be Incoherent
by Bernard Murphy on 01-01-2016 at 7:00 am

The advantage of working with cache memory is the great boost in performance you can get from working with a local high-speed copy of chunks of data from main memory. The downside is that you are messing with a copy; if another processor happens to be working in a similar area, there is a danger you can get out of sync when reading and writing… Read More


Lighting Up The Cloud

Lighting Up The Cloud
by Bernard Murphy on 12-30-2015 at 7:00 am

In our rush to imagine a world populated with IoT devices, tech advances at the top end of this ecosystem (the cloud) don’t seem to get much airtime. But this isn’t because they are limited to modest refinements. As one example, there is active technology development in connectivity around fiber-based communications within the… Read More


Tuning Analog IP for High Yield at SMIC

Tuning Analog IP for High Yield at SMIC
by Daniel Payne on 12-29-2015 at 12:00 pm

Analog IP is more difficult to design and optimize for a given process node compared to digital IP, so any automation for analog designers is always welcome. The engineers at SMIC in China have customers that design analog IP and often they need to know how to optimize it for a specific process, so I watched a presentation by Josh Yang,… Read More