If you’re headed to #53DAC (June 5-9 in Austin,TX) and are interested in learning more about FD-SOI, there will be lots of opportunities. Here’s a quick guide to get you started. … Read More
Electronic Design Automation
Layout Pattern Matching for DRC, DFM, and Yield Improvement
It is truly amazing to consider the advances in microelectronic process development, using 193i photolithography. The figure below is a stark reminder of the difference between the illuminating wavelength and the final imaged geometries. This technology evolution has been enabled by continued investment in mask data generation… Read More
Go Native – With Methodics at DAC in Austin
DAC is often a yearly reflection point for the companies that exhibit and attend. For the innovators it is an opportunity to look back and see a year of progress and development. Fortunately, this is the case for Methodics, which has had a strong year both in terms of business and technical development. Though, we easily see how these… Read More
Why USB 3.1 Certification is a “Must Have”?
USB 3 protocol is now height years old, but USB 3.1 is much more recent (2014). The adoption behavior for USB protocol is unique, as USB 2.0 bandwidth (480 Mbps) is largely enough for certain applications. Nevertheless we have seen the sales for USB 3 IP passing the USB 2 in value during 2014, and the total USB IP segment becoming the … Read More
DRC Concept for IP Qualification and SoC Integration
In the history of semiconductor design and manufacturing, the age-old concept of DRC rule-deck qualification for handshake between design and manufacturing still applies strongly to produce working silicon. In fact, DRC clean GDSII works as the de facto golden gate between a design and a foundry for manufacturing the chip for… Read More
Aart de Geus, Technomics and #53DAC
The number one EDA+IP vendor in our industry today is Synopsys, and their eloquent leader is Aart de Geus, so I expect that the Monday interview at #53DAC on June 6th will be well attended and worthwhile to witness in the DAC Pavilion, start time is 11:30AM, so arrive early to get a seat. One of Aart’s coined words is Technomics,… Read More
Six Reasons to Visit Cadence at #53DAC this Year in Austin
For bloggers like myself spending four days at #53DAC is almost a non-stop blur of activity, visiting EDA vendors, IP providers and foundries to learn about what’s happening in our semiconductor industry. Cadence is both an EDA vendor and IP provider, so DAC is a great showcase for them to tell us what’s new in 2016 and… Read More
What the #3 EDA company is showing at #53DAC this year
I live in Tualatin, Oregon just a few miles away from the corporate headquarters of the #3 EDA company in the world, Mentor Graphics. Since DAC is fast approaching, I thought it would be useful to give you a quick overview of what Mentor is going to be talking about in Austin, Texas during June 5-9. … Read More
Power Noise Sign-off at #53DAC
When I hear the company name of ANSYS the first EDA tool category that comes to mind is power noise sign-off. Going to DAC is a great way to find out what’s new with EDA, IP and foundries. There are three places that you can find ANSYS at DAC this year:… Read More
How TSMC Tackles Variation at Advanced Nodes
The design community is always hungry for high-performance, low-power, and low-cost devices. There is emergence of FinFET and FDSOI technologies at ultra-low process nodes to provide high-performance and low-power requirements at lower die-size. However, these advanced process nodes are prone to new sources of variation.… Read More
AI RTL Generation versus AI RTL Verification