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EDA

Electronic Design Automation

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Aldec Rounds Out ALINT-PRO Checker

Aldec Rounds Out ALINT-PRO Checker
by Bernard Murphy on 02-16-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor… Read More

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Using HSPICE StatEye to Tackle DDR4 Rail Jitter

Using HSPICE StatEye to Tackle DDR4 Rail Jitter
by Tom Simon on 02-15-2017 at 12:00 pm
Categories: EDA, Synopsys

The world is a risky place, according to Scott Wedge, Principal R&D Engineer at Synopsys, who presented at the Synopsys HSPICE SIG on Feb 2[SUP]nd[/SUP] in Santa Clara. Indeed, the world circuit designers face can be uncertain. Dealing with risk and departure from ideal was a main theme in the fascinating talks at this dinner… Read More

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Making Functional Simulation Faster with a Parallel Approach

Making Functional Simulation Faster with a Parallel Approach
by Daniel Payne on 02-14-2017 at 12:00 pm
Categories: Cadence, EDA

I’ll never forgot working at Intel on a team designing a graphics chip when we wanted to simulate to ensure proper functionality before tapeout, however because of the long run times it was decided to make a compromise to speed things up by reducing the size of the display window to just 32×32 pixels. Well, when first silicon… Read More

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Qorvo Uses ClioSoft to Bring Design Data Management to RF Design

Qorvo Uses ClioSoft to Bring Design Data Management to RF Design
by Mitch Heins on 02-13-2017 at 12:00 pm
Categories: Cliosoft, EDA

A couple weeks ago I gave a heads-up about a webinar that was being hosted by ClioSoft, Qorvo and Keysight. The topic of the webinar was how to manage custom RF designs across multiple design teams and CAD flows. The webinar was held on February 1st and included presentations by Marcus Ray of Qorvo and Michele Azarian of Keysight.

Much… Read More

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CEO Interview: Amit Gupta of Solido Design

CEO Interview: Amit Gupta of Solido Design
by Daniel Nenni on 02-13-2017 at 7:00 am
Categories: CEO Interviews, EDA, FD-SOI, FinFET, Solido

Solido Design Automation is rapidly making a name for itself in EDA. Amit Gupta is founder and CEO of Solido Design Automation, based in Saskatoon, Canada. You should also know that Solido is one of the founding members of SemiWiki.com. In the last six years we have published 44 Solido related blogs that have racked up more than 200,000… Read More

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DVCon San Jose February 27th – March 2nd

DVCon San Jose February 27th – March 2nd
by Bernard Murphy on 02-10-2017 at 7:00 am
Categories: EDA, Events

DVCon is fast approaching, less than 3 weeks away. As a verification geek, this must be one of my favorite conferences, so I’ll be there; you’ll see me at tutorials, presentations and wandering around the Exhibit hall. (Pictures here from the 2016 DVCon – many of the same attendees will be at this year’s conference after all :cool:)… Read More

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Notes from the Neural Edge

Notes from the Neural Edge
by Bernard Murphy on 02-09-2017 at 7:00 am
Categories: Automotive, Cadence, IoT, IP, Mobile

Cadence recently hosted a summit on embedded neural nets, the second in a series for them. This isn’t a Cadence pitch but it is noteworthy that Cadence is leading a discussion on a topic which is arguably the hottest in tech today, with this range and expertise of speakers (Stanford, Berkeley, ex-Baidu, Deepscale, Cadence… Read More

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FPGA Design Gets Real

FPGA Design Gets Real
by Tom Simon on 02-08-2017 at 12:00 pm
Categories: EDA, FPGA, Synopsys

FPGA’s have become an important part of system design. It’s a far cry from how FPGA’s started out – as glue logic between discrete logic devices in the early days of electronic design. Modern day FPGA’s are practically SOC’s in their own right. Frequently they come with embedded processor cores, sophisticated IO cells, DSP,… Read More

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Aspirational Congruence

Aspirational Congruence
by Bernard Murphy on 02-07-2017 at 7:00 am
Categories: Cadence, EDA, Prototyping

When talking to suppliers about their products, conversation tends to focus heavily on what they already have and why it is the answer to every imaginable need in their space. So it’s refreshing when a vendor wants to talk about where customers want to go without claiming they already have the answer wrapped up in a bow. I recently … Read More

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CTO Interview: Peter Theunis of Methodics

CTO Interview: Peter Theunis of Methodics
by Daniel Nenni on 02-06-2017 at 7:00 am
Categories: EDA, Perforce

Fascinated by computers at a very young age, Peter got his degree in Computer Science and was brought to the Bay Area via AIESEC Berkeley’s student exchange program to write his thesis. He has now more than 15 years of professional experience in software engineering, large scale systems architecture and data center engineering… Read More