Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Cadence Design Systems @ #54DAC!

Cadence Design Systems @ #54DAC!
by Daniel Nenni on 06-11-2017 at 8:00 am

This year Cadence Design Systems is showcasing system design enablement in their booth, capitalizing on the industry shift from naked chip design to system level chip design. Apple started it with making the chips inside the iProducts as part of the system and now other systems companies are looking to take more control over their… Read More


Mentor a Siemens Business @#54thDAC

Mentor a Siemens Business @#54thDAC
by Daniel Nenni on 06-11-2017 at 7:00 am

This year the Mentor booth will be quite interesting now that they are part of Siemens. I expect zero changes to their DAC presence but we shall see. It will certainly be good to see Wally again. More importantly, I will be afforded the opportunity to talk personally with both Wally Rhines, CEO of Mentor ANDChuck Grindstaff executiveRead More


Photonics at DAC – Integrated Electronic/Photonic Design Flow to be Presented at Cadence Theater

Photonics at DAC – Integrated Electronic/Photonic Design Flow to be Presented at Cadence Theater
by Mitch Heins on 06-09-2017 at 12:00 pm


I recently wrote an article on SemiWiki talking about the integrated Electronic/Photonic Design Automation (EPDA) flow that is being developed by Cadence Design Systems, Lumerical Solutions and PhoeniX Software and how that flow is now expanding into the system level through SiP (system in package) techniques.

Up till recently,… Read More


Simplifying Requirements Tracing

Simplifying Requirements Tracing
by Bernard Murphy on 06-09-2017 at 7:00 am

Requirements traceability is a necessary part of any top-down system specification and design when safety or criticality expectations depend on tightly-defined requirements for subsystems. Traceability in this context means being able to trace from initial documented requirements down through specification and datasheet… Read More


System Implementation Connectivity Verification and Analysis, Including Advanced Package Designs

System Implementation Connectivity Verification and Analysis, Including Advanced Package Designs
by Tom Dillinger on 06-08-2017 at 4:00 pm

Regular Semiwiki readers are aware of the rapid emergence of various (multi-die) advanced package technologies, such as: FOWLP (e.g., Amkor’s SWIFT, TSMC’s InFO); 2D die placement on a rigid substrate (e.g., TSMC’s CoWoS); and, 2.5D “stacked die” with vertical vias (e.g., any of the High Bandwidth Memory,… Read More


CCIX Protocol Push PCI Express 4.0 up to 25G

CCIX Protocol Push PCI Express 4.0 up to 25G
by Eric Esteve on 06-08-2017 at 12:00 pm

The CCIX consortium has developed the Cache Coherent Interconnect for Accelerators (X) protocol. The goal is to support cache coherency, allowing faster and more efficient sharing of memory between processors and accelerators, while utilizing PCIe 4.0 as transport layer. With Ethernet, PCI Express is certainly the most popular… Read More


EDA Powered by Machine Learning panel, 1-on-1 demos, and more!

EDA Powered by Machine Learning panel, 1-on-1 demos, and more!
by Daniel Nenni on 06-07-2017 at 12:00 pm

DAC is upon us again! The Design Automation Conference holds special meaning to me as it was the first technical conference I attended as a semiconductor professional, or professional anything for that matter. That was 33 years ago and I have not missed one since. This year my wife and I both will be walking the DAC floor and it would… Read More


Webinar: How RTL Design Restructuring Helps Meet PPA

Webinar: How RTL Design Restructuring Helps Meet PPA
by Bernard Murphy on 06-07-2017 at 7:00 am

To paraphrase an Austen line, it is a truth universally acknowledged that implementation, power intent and design hierarchy don’t always align very well. Hierarchy is an artifact of legacy structure, reuse and division of labor, perhaps well-structured piecewise for other designs but not necessarily so for the design you now… Read More


AI Being Used from Probing to Simulation

AI Being Used from Probing to Simulation
by Daniel Payne on 06-06-2017 at 12:00 pm

The 54th annual DAC event is fast approaching, so I hope to see many of you in Austin on June 18-21. The phrases Machine Learning and AI are growing in all areas of software, so I’m glad to see it appearing in more EDA tool offerings over the past year or so. One company that I plan to visit at DAC is Platform Design Automation because… Read More