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Portable Stimulus Standard, What’s New from Cadence

Portable Stimulus Standard, What’s New from Cadence
by Daniel Payne on 09-27-2017 at 12:00 pm

I’ve been hearing about the Portable Stimulus Standard (PSS) since DAC 2016, so it’s helpful to get an update from EDA vendors on what their involvement level is with this emerging standard and how they see it helping design and verification engineers. Earlier in September I scheduled a conference call with Cadence… Read More


CDNLive Boston Keynote Address Highlights Emergence of Silicon Photonics

CDNLive Boston Keynote Address Highlights Emergence of Silicon Photonics
by Mitch Heins on 09-27-2017 at 7:00 am

I had the pleasure of being able to attend the CDNLive event held in the Boston, MA area last month and I was pleasantly surprised to see that Cadence highlighted Silicon Photonics as one of its Keynote topics. MIT Professor Duane Boning gave an excellent overview of the current state of silicon photonics and why he believes it is time… Read More


How to Avoid Jeopardizing SoC Security when Implementing eSIM?

How to Avoid Jeopardizing SoC Security when Implementing eSIM?
by Eric Esteve on 09-26-2017 at 12:00 pm

Smart card business is now more than 25 years old, we can assess that the semiconductor industry is able to protect the chips used for smart card or SIM application with a very good level (unfortunately, it’s very difficult to get access to the fraud percentage linked with smart cards, as bankers really don’t like to communicate on… Read More


Verification Trends: 2016

Verification Trends: 2016
by Bernard Murphy on 09-26-2017 at 7:00 am

Periodically Mentor does us all a big favor by commissioning a survey of verification engineers across the world to illuminate trends in verification. This is valuable not only to satisfy our intellectual curiosity but also to help convince managers and finance mandarins that our enthusiasm to invest in new methods and tools … Read More


Semiconductor and EDA 2017 Update!

Semiconductor and EDA 2017 Update!
by Daniel Nenni on 09-25-2017 at 7:00 am

It really is an exciting time in semiconductors. The benchmarks on the new Apple A11 SoC and the Nvidia GPU are simply amazing. Even though Moore’s Law is slowing, the resulting chips are improving well above and beyond expectations, absolutely.

As I have mentioned before, non-traditional chip companies such as Apple, Amazon,… Read More


Walden Rhines on the Automotive Electronics Landscape

Walden Rhines on the Automotive Electronics Landscape
by Roger C. Lanctot on 09-23-2017 at 8:00 am

Mentor President and CEO Walden Rhines gave a comprehensive overview of the automotive electronics landscape at the Mentor Integrated Electrical Solutions Forum (IESF) in Plymouth, Mich., this week. A key focal point of Rhines’ comments was the twin industry disruptors: EVs and AVs.

A Texas Instruments alum, Rhines described… Read More


Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More


IoT SoCs Demand Good Data Management and Design Collaboration

IoT SoCs Demand Good Data Management and Design Collaboration
by Mitch Heins on 09-20-2017 at 12:00 pm

Design data management has always been important. Board designers have known this for decades as they had to have ways to keep all their discreet components organized and understood. Sourcing components is not easy as it means hours of reading and reviewing specifications, finding reliable sourcing partners and understanding… Read More


Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+

Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+
by Mitch Heins on 09-20-2017 at 12:00 pm

Open Silicon hosted a webinar today focusing on their High Bandwidth Memory (HBM) IP-subsystem product offering. Their IP-subsystem is based on the HBM2 standard and includes blocks for the memory controller, PHY and high-speed I/Os, all targeted to TSMC 16nm FF+ process. The IP-subsystem supports the full HBM2 standard with… Read More


Improved Memory Design, Characterization and Verification

Improved Memory Design, Characterization and Verification
by Daniel Payne on 09-19-2017 at 12:00 pm

My IC design career started out with DRAM design, characterization and verification back in the 1970’s, so I vividly recall how much SPICE circuit simulation was involved, and how little automation we had back in the day, so we tended to cobble together our own scripts to help automate the process a bit. With each new process… Read More