BroncoAI DVCon100x800 FIX
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Cadence Summit Highlights Automotive Market Dynamics and System Enablement

Cadence Summit Highlights Automotive Market Dynamics and System Enablement
by Camille Kokozaki on 12-04-2018 at 12:00 pm

Cadence held a well-attended Automotive Summit where Cadence presented an overview of their solution and system enablement along with industry experts and established or startup companies sharing their perspective and product features from autonomous driving, LiDAR, Radar, thermal imaging, sensor imaging, and AI.… Read More


Improving Library Characterization with Machine Learning!

Improving Library Characterization with Machine Learning!
by Daniel Nenni on 12-04-2018 at 7:00 am

For SOC designers that are waiting for library models the saying “give me liberty or give me death” is especially apropos. Without libraries to support the timing flow, SOC design progress can grind to a halt. As is often the case, more than just a few PVT corners are needed. Years ago, corners were what the term sounded like – the 4 corners… Read More


Car Vandals Eschew Crowbars

Car Vandals Eschew Crowbars
by Tom Simon on 12-03-2018 at 12:00 pm

It used to be that automotive theft and crime was perpetrated with a crowbar. Now with increased electronics content, car designer and owners need to worry about electronic threats. Anywhere there is a communication link or a processor, there are potential threats to the security of the car. The range of these threats covers everything… Read More


Catapult Design Checker Finds Coding Errors Before High Level Synthesis

Catapult Design Checker Finds Coding Errors Before High Level Synthesis
by Camille Kokozaki on 11-26-2018 at 12:00 pm

In a recent whitepaper Gagandeep Singh, Director of Engineering at Mentor, a Siemens Business outlines a flow using Catapult Design Checker that helps in early detection of coding errors as many companies are turning to High-Level Synthesis (HLS) methodology. This requires that high -level C++ models are correct, that ambiguities… Read More


Design Compiler – Next Generation

Design Compiler – Next Generation
by Alex Tan on 11-20-2018 at 12:00 pm

Back in 1986, Synopsys started out with a synthesis product by name of SOCRATES, which stands for Synthesis andOptimization ofCombinatorial logic usingRule-basedAndTechnology independentExpertSystem. It is fair to say that not many designers know that was the birth name of what eventually turns out to be a very successful… Read More


Webinar: Tanner and ClioSoft Integration

Webinar: Tanner and ClioSoft Integration
by Alex Tan on 11-20-2018 at 7:00 am

A fusion of digital and analog IC circuits, mixed signal ICs are key components to many applications including IoTs, automotive, communications and consumer electronics –acting as enabler to bidirectional conversion of signals between analog domain derived from various audio, temperature and visual sensors to digital… Read More


Using IP in a SoC Compliant with ISO 26262

Using IP in a SoC Compliant with ISO 26262
by Daniel Payne on 11-19-2018 at 12:00 pm

The automotive segment is being well served by semiconductor suppliers of all sizes because of the unit volumes, and the constant push to automate more of the driving decisions to silicon and software can raise lots of questions about safety, reliability and trust. Fortunately the ISO standards body has already put in place a functional… Read More


I Thought that Lint Was a Solved Problem

I Thought that Lint Was a Solved Problem
by Daniel Nenni on 11-16-2018 at 12:00 pm

A few months back, we interviewed Cristian Amitroaie, the CEO of AMIQ EDA. We talked mostly about their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and how it helps design and verification engineers develop code in SystemVerilog and several other languages. Cristian also mentioned… Read More


Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform

Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform
by Daniel Nenni on 11-15-2018 at 12:00 pm

The rapidly increasing complexity of today’s designs, combined with schedule pressure to deliver innovative products to market as quickly as possible, strains engineering resources to the limit, often to the point of breaking. As a result, 17% of all projects get canceled, and another 28% miss their target release date (Source:… Read More