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Fusion Synthesis for Advanced Process Nodes

Fusion Synthesis for Advanced Process Nodes
by Alex Tan on 11-13-2018 at 12:00 pm

Synopsys recently unleashed Fusion Compiler™, a new RTL-to-GDSII product that enables a data-driven design implementation by revamping Design Compiler architecture and leveraging the successful Fusion Technology –seamlessly fusing the logical and physical realms to produce predictable QoR. It is a long-awaited… Read More


DAC 2019 to Host the Second System Design Contest!

DAC 2019 to Host the Second System Design Contest!
by Daniel Nenni on 11-13-2018 at 7:00 am

Interested in showing off your talent in developing deep learning algorithms on embedded hardware platforms for solving real-world problems? Join the second System Design Contest (SDC) at the 56[SUP]th[/SUP] Design Automation Conference in 2019!… Read More


Webinar: NVIDIA Talks High Quality Metrics in Power Integrity Signoff

Webinar: NVIDIA Talks High Quality Metrics in Power Integrity Signoff
by Bernard Murphy on 11-09-2018 at 12:00 pm

There’s a familiar saying that you can’t improve what you can’t measure. Taking that one step further, the more improvement you want, the more accurately you have to measure. This become pretty important when you’re building huge designs in advanced technologies. Margins are a lot tighter all round and use-cases are massively… Read More


Coupled Electro-thermal Analysis Essential for PowerMOS Design

Coupled Electro-thermal Analysis Essential for PowerMOS Design
by Tom Simon on 11-08-2018 at 12:00 pm

Power device designers know that when they see a deceptively simple pair of PowerMOS device symbols in the output stage of a power converter circuit schematic, they are actually looking at a massively complex network of silicon and metal interconnect. The corresponding physical devices can have a total device W on the order of … Read More


Emulation from In Circuit to In Virtual

Emulation from In Circuit to In Virtual
by Bernard Murphy on 11-08-2018 at 7:00 am

At a superficial level, emulation in the hardware design world is just a way to run a simulation faster. The design to be tested runs on the emulator, connected to whatever test mechanisms you desire, and the whole setup can run many orders of magnitude faster than it could if the design was running inside a software simulator. And … Read More


Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?

Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?
by Eric Esteve on 11-06-2018 at 6:00 am

Ambiq Micro has built a family of voice processing MCU dedicated to battery powered, energy sensitive systems, supporting mobile application like wearable. The company is facing two strong challenges: support computationally intensive processing (NN-based far field) and speech recognition algorithms, while offering … Read More


The Changing Face of IP Management

The Changing Face of IP Management
by Alex Tan on 11-05-2018 at 11:00 am


Aristotle once said “The whole is greater than the sum of its parts”. The notion of synergism echoes the importance of leveraging design IPs to the maximum extent with the rest of the system under development, in order to ensure a successful SoC design outcome in a shorter development cycle.

SoC design cost and entry point
For over… Read More


Designing Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP

Designing Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP
by Camille Kokozaki on 11-01-2018 at 12:00 pm

As new automotive Advanced Driver Assistance System (ADAS) based product releases intensifies while a more stringent set of safety requirements are mandated, it is not surprising that subsystem and electronic suppliers are looking for pre-designed and ISO 26262 certified IP that can address both imperatives of schedule and… Read More


Mentor’s Busy ITC and Major Test Product Updates

Mentor’s Busy ITC and Major Test Product Updates
by Tom Simon on 10-31-2018 at 1:00 pm

In conjunction with the 2018 International Test Conference, Mentor has several interesting test announcements. They also have a busy round of technical activities, including a number of technical papers, presentations, tutorials and a poster from a major customer about using Mentor. I’d like to touch on the two product related… Read More


Parasitic Extraction for Advanced Node and 3D-IC Designs

Parasitic Extraction for Advanced Node and 3D-IC Designs
by Alex Tan on 10-31-2018 at 7:00 am

Technology scaling has made positive impacts on device performance, while creating challenges on the interconnects and the fidelity of its manufactured shapes. The process dimension scaling has significantly increased metal and via resistance for advanced nodes 7nm and onward, as shown in figures 1a,1b. Similar to a fancy… Read More